• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.294-301
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• 2017

This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.712-719
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• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.26-32
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• 2017

This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.1-8
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• 2007

A wideband continuous-time sigma delta modulator for wireless application is implemented in 130nm CMOS. The SNR for small input signal is improved using a proposed adaptive quantizer which can effectively scale the quantization level. The modulator comprises a second-order loop filter for low power consumption, 4-bit quantizer and DAC for low jitter sensitivity and high linearity. Designed circuit achieves peak SNR of 51.36B with 10MHz signal Bandwidth and 320MHz sampling frequency dissipating 30mW.