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http://dx.doi.org/10.5573/ieie.2017.54.1.026

Low Power Discrete-Time Incremental Delta Sigma ADC with Passive Integrator  

Oh, Goonseok (Department of Electronics Engineering, Konkuk University)
Kim, Jintae (Department of Electronics Engineering, Konkuk University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.54, no.1, 2017 , pp. 26-32 More about this Journal
Abstract
This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.
Keywords
Discrete Time Delta-Sigma Modulator; Low Power; Passive Integrator;
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