• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.702-706
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• 1996

The King Sejong's Striking water-clock was named for its distictive day and night time announcing system. Its time announcing system generates acoustic and visual signals for the twelve double hour, and combinations of two different acoustic signals for the five night watches, The mechanism of this signal generation system is triggered by a copper ball which is mechanically digitized time keeping signal, and is generated from the water clock. The time announcing system consisted four parts: 1) the mechanical amplifier which changes small copper to heavy steel ball, 2) day time announcing system, 3) night time announcing system, 4) sounding mechanism. The time announcing system of King Seong's Striking Clepsidra is remotely related to the Arabic clock system, however, it does have world-widely distictive mechanisms of its era, such as mechanical amplifier, self-weight rachet mechanism, and resetable mechanical computer etc.

• ETRI Journal
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• 제37권4호
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권8호
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Journal of Astronomy and Space Sciences
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• 제30권2호
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• pp.113-121
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• 2013

Heumgyeonggaknu is a water-hammering type automatic water clock which was made by Jang Yeong-Sil in 1438. The water clock that is located in Heumgyeonggaknu consists of Suho which is equipped with 2-stage overflow. Constant water wheel power is generated by supplying a fixed amount of water of Suho to Sususang, and this power is transferred to each floor at the same time. The 1st floor rotation wheel of Gasan consists of the operation structure which has the shape of umbrella ribs. The 2nd floor rotation wheel is made so that the 12 hour signal, Gyeong-Jeom signal, and Jujeon constitute a systematic configuration. The 3rd floor rotation wheel is made so that the signal and rotation of Ongnyeo and four gods can be accomplished. Based on the above conceptual design, this paper analyzed the internal signal generation and power transmission of Heumgyeonggaknu.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• 전기전자학회논문지
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• 제15권1호
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• pp.23-28
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• 2011

본 논문에서는 CMOS 회로를 이용한 스프레드 스펙트럼 클록 발생기(SSCG)를 제안하고 구현하였다. 지연고정루프(DLL)의 저역통과필터(LPF)에 스프레드 스펙트럼 클럭 변조 로직에 의해 조절되는 전하펌프를 연결하여 전압 제어지연로직(VCDL)에 가해지는 제어전압을 조절함으로써 주파수의 변화를 유도하는 방법을 사용하였다. 이와 같은 구조에서는 변조 비율을 조절하기 위한 부가적인 회로가 필요없기 때문에 레이아웃 면적이 작아지게 되고 전력소모가 작아지는 장점을 갖는다. 스프레드 스펙트럼 클록 발생기는 UMC 0.25um 공정을 이용하여 시뮬레이션 및 레이아웃을 수행하였으며 전체 면적은 290um${\times}$120um^2 이다.

• 전자공학회논문지A
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• 제30A권7호
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• pp.75-81
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• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.

• 전기학회논문지
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• 제56권6호
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• ETRI Journal
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• 제33권6호
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• pp.841-848
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• 2011

A signal-to-noise ratio (SNR) enhancement algorithm using multiple chirp symbols with clock drift is proposed for accurate ranging. Improvement of the ranging performance can be achieved by using the multiple chirp symbols according to Cramer-Rao lower bound; however, distortion caused by clock drift is inevitable practically. The distortion induced by the clock drift is approximated as a linear phase term, caused by carrier frequency offset, sampling time offset, and symbol time offset. SNR of the averaged chirp symbol obtained from the proposed algorithm based on the phase derotation and the symbol averaging is enhanced. Hence, the ranging performance is improved. The mathematical analysis of the SNR enhancement agrees with the simulations.