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A Low Power Multi Level Oscillator Fabricated in $0.35{\mu}m$ Standard CMOS Process  

Chai Yong-Yoong (계명대 공대 전자공학과)
Yoon Kwang-Yeol (계명대 공대 전자공학과)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers C / v.55, no.8, 2006 , pp. 399-403 More about this Journal
Abstract
An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.
Keywords
Multi Level Oscillator; Analog Memory; PLL; VCO;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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