1 |
W. D. Brown and J. E. Brewer, 'Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices,' IEEE New York, pp.6-9, 1998
|
2 |
K. Ohsaki, N. Asarnoto, and S. Takagaki, 'A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,' IEEE J. Solid State circuit, Vol. 29, No.3, pp, 311-316, Mar. 1994
DOI
ScienceOn
|
3 |
D. H. Wolaver, 'Phase-Locked Loop Circuit Design', Prentice Hall, New Jersey, pp.9-106, 1991
|
4 |
이승훈, 김범섭, 송민규, 최중호, CMOS 아날로그/혼성모드 집적시스템 설계(下). 시그마프레스, pp.257-304, 1999
|
5 |
R. Harrison, A. Bragg, and P. Hasler, 'A CMOS Programmable Analog Memory-Cell Array Using Floating-Gate Circuits,' IEEE Trans. on circuits and systems, Vol. 48, No.1, pp. 4-11, Jan. 2001
DOI
ScienceOn
|
6 |
Y. Y. Chai, 'A Analog Memory Implemented with a Special Layout Injector,' IEEE Journal of Solid-State Circuits, Vol. 32, pp.856-859, June 1996
DOI
ScienceOn
|
7 |
채용웅, 정동진, '0.35um 싱글폴리 표준 CMOS공정에서 제작된 아날로그 메모리 셀의 프로그래밍 특성', 전기학회논문지, VOL.53D, NO.6, pp.425-432, June 2004
과학기술학회마을
|
8 |
R. Harrison, P. Hasler,B. A. Minch, 'Floating-Gate CMOS Analog Memory Cell Array,' in Proc. Int. Symp. Circuits and Systems, Monterey, CA, 1998
DOI
|