1 |
Kihyuk Sung and Lee-Sup Kim, 'A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register' IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 39, NO. 11, NOVEMBEH 2004
DOI
ScienceOn
|
2 |
Kuo-Hsing Cheng; Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su, 'A phase-detect synchronous mirror delay for clock skew-compensation circuits', Circuits and Systems, ISCAS 2005. IEEE International Symposium. Page(s):1070-1073 Vol. 2, 23-26 May 2005
DOI
|
3 |
J. M. Rabaey 'Digital Integrated Circuits' Prentice Hall, Page(s):193-203
|
4 |
Takanori Saeki, et al, 'A 2.5ns Clock Access, 250-MHz, 256-Mb SDHAM with Synchronous Mirror Delay,' IEEE J. Solid-State Circuits, vol. 31, no. 11, Page(s): 1656-1668
DOI
ScienceOn
|
5 |
Toru Ogawa and Kenji Taniguchi, 'A 50% Duty-Cycle Correction Circuit for PLL output,' IEEE International Symposium on Circuits and Systems, vol.: 4, Page(s): IV-21 -IV-24. May 2002
DOI
|
6 |
Yi-Ming Wang, Jinn-Shyan Wang, 'An All Digital 50% Duty-Cycle Corrector,' ISCAS Page(s): II925-II928. 2004
|