• 대한전자공학회논문지SD
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• 제40권9호
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• 대한전자공학회논문지SD
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• 제41권7호
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• pp.21-29
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• 2004

본 논문에서는 Dual oxide를 갖는 Nano-scale CMOSFET에서 각 소자의 Hot carrier 특성을 분석하여 두 가지 중요한 결과를 나타내었다. 하나는 NMOSFET Thin/Thick인 경우 CHC stress 보다는 DAHC stress에 의한 소자 열화가 지배적이고, Hot electron이 중요하게 영향을 미치고 있는 반면에, PMOSFET에서는 특히 Hot hole에 의한 영향이 주로 나타나고 있다는 것이다. 다른 하나는, Thick MOSFET인 경우 여전히 NMOSFET의 수명이 PMOSFET의 수명에 비해 작지만, Thin MOSFET에서는 오히려 PMOSFET의 수명이 NMOSFET보다 작다는 것이다. 이러한 분석결과는 Charge pumping current 측정을 통해 간접적으로 확인하였다. 따라서 Nano-scale CMOSFET에서의 NMOSFET보다는 PMOSFET에 대한 Hot camel lifetime 감소에 관심을 기울여야 하며, Hot hole에 대한 연구가 진행되어야 한다고 할 수 있다.

• 대한전자공학회논문지
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• 제25권2호
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• pp.182-187
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• 1988

Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.749-752
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• 2014

Spacer 유무와 핀 폭, 채널길이에 따른 n채널 MuGFET의 단채널 및 열화 특성을 비교 분석 하였다. 사용된 소자는 핀 수가 10인 Tri-Gate이며 Spacer 유무에 따른 핀 폭이 55nm, 70nm인 4종류이다. 측정한 소자 특성은 DIBL, subthreshold swing, 문턱전압 변화 (이하 단채널 현상)과 소자열화이다. 측정 결과, 단채널 현상은 spacer가 있는 것이 감소하였고, hot carrier degradation은 spacer가 있고 핀 폭이 작은 것이 소자열화가 적었다. 따라서, spacer가 있는 LDD(Lightly Doped Drain) 구조이며 핀 폭이 작은 설계방식이 단채널 현상 및 열화특성에 더욱 바람직하다.

• 전자공학회논문지A
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• 제28A권12호
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• 대한전자공학회논문지
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• 제25권7호
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• pp.780-790
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• 1988

We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

• 대한전자공학회논문지SD
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• 제49권1호
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• pp.8-14
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• 2012

전체 채널 폭은 같지만 핀 수와 핀 폭이 다른 n-채널 MuGFET의 특성을 측정 비교 분석하였다. 사용된 소자는 Pi-gate 구조의 MuGFET이며 핀 수가 16이며 핀 폭이 55nm인 소자와 핀 수가 14이며 핀 폭이 80nm인 2 종류의 소자이다. 측정 소자성능은 문턱전압, 이동도, 문턱전압 roll-off, DIBL, inverse subthreshold slope, PBTI, hot carrier 소자열화 및 드레인 항복전압 이다. 측정 결과 핀 폭이 작으며 핀 수가 많은 소자의 단채널 현상이 우수한 것을 알 수 있었다. PBTI에 의한 소자열화는 핀 수가 많은 소자가 심하며 hot carrier에 의한 소자열화는 비슷한 것을 알 수 있었다. 그리고 드레인 항복 전압은 핀 폭이 작고 핀 수가 많은 소자가 높은 것을 알 수 있었다. 단채널 현상과 소자열화 및 드레인 항복전압 특성을 고려하면 MuGFET소자 설계 시 핀 폭을 작게 핀 수를 많게 하는 것이 바람직하다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1065-1070
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• 2007

The effects of hot carriers and self-heating on the electrical stability of p-channel TFTs have been analysed combining experimental data and numerical simulations. While hot carrier effects were shown not to induce appreciable degradation, self-heating related instability was found to more seriously affect the device characteristics. New models have been developed to explain the reported results.

• 전자공학회논문지A
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• 제33A권4호
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• pp.129-135
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• 1996

In this paper, the hot carrier effect and device degradation of deep submicrometer SC-PMOSFETs have been measured and characterized. It has been shown that the substrate current of a 0.15$\mu$m PMOSFET increases with increasing of impact ionization rate, and the impact ionization rate is a function of the gate length and gate bias voltage. Correlation between gate current and substrate current is investigated within the general framework of the lucky-electron. It is found that the impact ionization rate increases, but the device degradation is not serious with decreasing effective channel length. SCIHE is suggested as the possible phusical mechanism for enhanced impact ionization rate and gate current reduction. Considering the hot carrier induced device degradation, it has been found that the maximum supply voltage is about -2.6V for 0.15$\mu$m PMOSFET.