• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.929-932
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• 1993

A fuzzy microcontroller is presented implementing a simplified inference mechanism. Fuzzification, rule composition and defuzzification are carried out by means of (basically) analog current-mode CMOS circuits operating in strong inversion. Also a voltage interface is provided with the external world. Combining analog and digital techniques allow a programming capability.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• 전기학회논문지P
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• 제58권4호
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• ETRI Journal
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• 제44권5호
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• Journal of Information Display
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• 제5권4호
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• pp.1-6
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• 2004

In this paper, we investigate on the characteristics of poly-Si TFTs reuired for the implementation of analog circuits to be integrated with System-on-Glass (SoG). Matching requirements in terms of resistor values, threshold voltage and mobility of poly-Si TFTs are derived as a function of the resolution of display system. Effective mobility of poly-Si TFTs required for the realization of source driver is analyzed for various panel sizes.

• 대한임베디드공학회논문지
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• 제4권1호
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• pp.23-28
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• 2009

Testing of analog(and mixed-signal) circuits has been a difficult task for test engineers and effective test techniques to solve these problems are required. This paper develops a new technique which increases fault detection and diagnosis rates for analog circuits by using extended MTSS (Modified Time Slot Specification) technique based on MTSS proposed by the author. High performance current sensors with digital outputs are used as core components for these techniques. A fault diagnosis structure with minimal hardware overhead in ATE is also described.

• 전기학회논문지
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• 제59권8호
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• pp.1489-1496
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• 2010

A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.

• 한국멀티미디어학회논문지
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• 제10권10호
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• pp.1260-1270
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• 2007

테스트 기술자들에게 아날로그 회로(또는 혼합신호 회로)의 테스트와 진단은 여전히 어려운 문제여서 이를 해결할 수 있는 효과적인 테스트 방법이 크게 요구된다. 본 논문에서는 time slot specification(TSS) 기반의 내장 전류감지기(Built-in Current Sensor)를 이용한 새로운 아날로그 회로의 테스트 기법을 제안한다. 또한 TSS에 기반 하여 고장 위치를 찾아내고 고장의 종류를 구별해 내는 방법을 제시한다. TSS 기법과 함께 제안하는 내장 전류감지기는 높은 고장 용이도와 높은 고장 검출을 그리고 아날로그 회로내 강고장과 약고장에 대한 높은 진단율을 갖는다. 제안하는 방법에서는 주출력과 전원단자등을 테스트 포인트로 사용하고 전류감지기를 자동 테스트 장치(Automatic Test Equipment)에 구성하므로써 테스트 포인트 선택과정의 복잡도를 줄일 수 있다. 내장 전류 감지기의 디지털 출력은 아날로그 IC 테스트를 위한 내장 디지털 테스트 모듈과 쉽게 연결된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.