The Transactions of the Korean Institute of Electrical Engineers P (전기학회논문지P)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Parallel Structure of Viterbi Decoder for High Performance of PRML Signal

PRML신호용 고성능 Viterbi Decoder의 병렬구조

  • 서범수 (전북대학교 로봇비젼연구실) ;
  • 김종만 (전남도립대 전기에너지시스템과) ;
  • 김형석 (전북대학교 전자정보공학부)
  • Published : 2009.12.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

Keywords

References

  1. Sun-How Jiang and Feng-Hsing Lo, "PRML process of multilevel run length-limited modulation recoding on optical disk, "IEEE Trans. On magnetism, Vol.41. no.2 pp.1070-1072, Feb.2005 https://doi.org/10.1109/TMAG.2004.842015
  2. Hyun-Soo Park et al, "Simplified error generation scheme for LMS adaptation of PRML channel," Proceeding of Satellite ISOM, pp. 70-71, 2000
  3. G. D. Forney, JR. "The Viterbi Algorithm," Proc. of the IEEE, vol. 61, No. 3, Mar. 1973
  4. Gene sonu et al, "Partial-Response Maximum -Likelihood core development for a CD/DVD controller integrated circuits," IEEE transaction on Magnetics, Vol. 37, No. e, March 2001
  5. H. Kobayashi and D.T. Tang, "Application of patial response channel coding to magnetic recording system, "IBM journal of research and development. pp.368-375, 1970
  6. R. G. Yamasaki et al, "A 72Mb/s PRML disk drive channel chip with an analog sampled data signal processor," in Dig. Tech. Papers ISSCC, Feb., pp. 278-279, 1994
  7. Jens Sparso. Henrik N Jorgenson," An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures," IEEE Ir. solid-State Ciucuit, vol. SC-26 no.2 pp.90-96 Feb. 1991 https://doi.org/10.1109/4.68122