Browse > Article
http://dx.doi.org/10.4218/etrij.2021-0203

Machine learning-based design automation of CMOS analog circuits using SCA-mGWO algorithm  

Vijaya Babu, E (Research Scholar, Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University Kakinada)
Syamala, Y (Department of Electronics and Communication Engineering, Gudlavalleru Engineering College)
Publication Information
ETRI Journal / v.44, no.5, 2022 , pp. 837-848 More about this Journal
Abstract
Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.
Keywords
algorithm; analog circuits; design automation; machine learning; optimization;
Citations & Related Records
연도 인용수 순위
  • Reference
1 K. Ueno et al., A 300 nW, 15 ppm/∘C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs, IEEE J. Solid-State Circuit 44 (2009), no. 7, 2047-2054.   DOI
2 R. A. Vural and T. Yildirim, Analog circuit sizing via swarm intelligence, AEU - Int. J. Electron. Commun. 66 (2012), no. 9, 732-740.   DOI
3 M. A. M. Majeed and S. R. Patri, An enhanced grey wolf optimization algorithm with improved exploration ability for analog circuit design automation, Turkish J. Electr. Eng. Comput. Sci. 26 (2018), 2605-2617.   DOI
4 P. Sarkar et al., Offset voltage minimization based circuit sizing of CMOS operational amplifier using whale optimization algorithm, J. Inf. Optim. Sci. 39 (2018), no. 1, 83-98.
5 S. Ghosh et al., Symbiotic organisms search algorithm for optimal design of CMOS two-stage Op-amp with nulling resistor and robust bias circuit, IET Circuits, Devices Syst. 13 (2019), 679-688.   DOI
6 B. De et al., An efficient design of CMOS comparator and folded cascode Op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm, Int. J. Mach. Learn. Cybern. 7 (2015), 1-20.
7 B. De et al., PSO With aging leader and challengers for optimal design of high speed symmetric switching CMOS inverter, Int. J. Mach. Learn. Cybern. 8 (2017), 1403-1422.   DOI
8 N. Mittal, U. Singh, and B. Sohi, Modified grey wolf optimizer for global engineering optimization, Appl. Comput. Intell. Soft Comput. 2016 (2016), 1-16.
9 M. A. M. Majeed and S. R. Patri, A hybrid of WOA and mGWO algorithms for global optimization and analog circuit design automation, COMPEL - Int. J. Comput. Math. Electr. Electron. Eng. 38 (2018), no. 1, 452-576.
10 R. A. Thakker, M. S. Baghini, and M. B. Patil, Low-power lowvoltage analog circuit design using hierarchical particle swarm optimization, in Proc. IEEE Int. Conf. VLSI Des. (New Delhi, India), Jan. 2009, pp. 427-432.
11 J. Kennedy and R. Eberhart, Particle swarm optimization, in Proc. ICNN'95 - Int. Conf. Neural Netw. (Perth, Australia), Nov. 1995, pp. 1942-1948.
12 R. Acar Vural and T. Yildirim, Swarm intelligence based sizing methodology for CMOS operational amplifier, in Proc. IEEE Int. Symp. Comput. Intell. Informatics (Budapest, Hungary), Nov. 2011, pp. 525-528.
13 V. Ceperic, Z. Butkovic, and A. Baric, Design and optimization of self-biased complementary folded cascode, in Proc. Med. Electrotech. Conf. (Melecon 2006), (Malaga, Spain), May 2006, pp. 145-148.
14 R. C. Eberhart and Y. Shi, Comparison between genetic algorithms and particle swarm optimization, in Evolutionary Programming VII, vol. 1447, Springer, Berlin, Heidelberg, Germany, 1998, pp. 611-616.
15 E. Tlelo-Cuautle, M. A. Valencia-Ponce, and L. G. de la Fraga, Sizing CMOS amplifiers by PSO and MOL to improve DC operating point conditions, Electronics 9 (2020), no. 6, article no. 1027, Available from: https://www.mdpi.com/2079-9292/9/6/1027   DOI
16 S. Mirjalili, S. M. Mirjalili, and A. Lewis, Grey wolf optimizer, Adv. Eng. Softw. 69 (2014), 46-61.   DOI
17 M. A. M. Majeed and P. S. Rao, Optimization of CMOS analog circuits using grey wolf optimization algorithm, in Proc. IEEE India Counc. Int. Conf. (INDICON), (Roorkee, India), Dec. 2017, pp. 1-6.
18 B. D. Liu, J. Y. Lee, and H. H. Wang, Parameter extraction and optimization for MOSFET models, Int. J. Electron. 63 (1987), no. 6, 873-884.   DOI
19 M. A. M. Majeed and P. S. Rao, Optimal design of CMOS amplifier circuits using whale optimization algorithm, in Communication, Networks and Computing, vol. 839, Springer, Singapore, Singapore, 2019, pp. 590-605.
20 P. Kumar and K. Duraiswamy, An optimized device sizing of analog circuits using particle swarm optimization, J. Comput. Sci. 8 (2012), 930-935.   DOI
21 G. Chandrasekaran et al., Test scheduling of system-on-chip using dragonfly and ant lion optimization algorithms, J. Intell. Fuzzy Syst. 40 (2021), 4905-4917.   DOI
22 M. Shams, E. Rashedi, and A. Hakimi, Clustered gravitational search algorithm and its application in parameter optimization of a low noise amplifier, Appl. Math. Comput. 258 (2015), 436-453.
23 M. Dehbashian and M. Maymandi-Nejad, A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique, Integration: The VLSI J. 56 (2016), 148-166.
24 M. Dehbashian and M. Maymandi-Nejad, An enhanced optimization kernel for analog IC design automation using the shrinking circles technique, Eng. Appl. Artif. Intell. 58 (2017), 62-78.   DOI
25 G. Chandrasekaran, S. Periyasamy, and K. P. Rajamanickam, Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques, Neural Comput. Appl. 32 (2020), 5303-5312.   DOI
26 S. Mirjalili, SCA: A sine cosine algorithm for solving optimization problems, Knowl.-Based Syst. 96 (2016), 120-133.   DOI