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http://dx.doi.org/10.5370/KIEE.2010.59.8.1489

Feed forward Differential Architecture of Analog Parallel Processing Circuits for Analog PRML Decoder  

Sah, Maheshwar Pd. (전북대 전자정보공학부 전자공학과)
Yang, Chang-Ju (전북대 전자정보공학부 전자공학과)
Kim, Hyong-Suk (전북대 전자정보공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.59, no.8, 2010 , pp. 1489-1496 More about this Journal
Abstract
A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.
Keywords
PRML; Analog parallel processing; Feed forward; Trellis processing;
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