• Title/Summary/Keyword: W_LSB

Search Result 122, Processing Time 0.029 seconds

A Study on the ADC for High Speed Data Conversion (고속 데이터 변환을 위한 ADC에 관한 연구)

  • Kim, Sun-Youb;Park, Hyoung-Keun
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.8 no.3
    • /
    • pp.460-465
    • /
    • 2007
  • In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

  • PDF

A CMOS Digital-to-Analog Converter to Apply a Newly-Developed Digital-to-Analog Conversion Algorithm (새로운 디지털-아날로그 변환알고리즘을 적용한 CMOS 디지털-아날로그 변환기)

  • 송명호
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.35C no.9
    • /
    • pp.57-63
    • /
    • 1998
  • This paper describes a CMOS digital-to-analog converter to apply a newly-developed digital-to-analog conversion algorithm. The CMOS digital-to-analog converter has been designed by using 1.2$\mu\textrm{m}$ MOSIS SCMOS parameter and simulated for the performance. The simulated results have shown that the digital-to-analog converter has 200MHz of the maximum conversion rate, 7.41mW of the DC power consumption, and ${\pm}$0.08LSB of INL and ${\pm}$0.098LSB of DNL in 8-b.

  • PDF

Design of High Speed Pipelined ADC for System-on-Panel Applications (System-on-Panel 응용을 위한 고속 Pipelined ADC 설계)

  • Hong, Moon-Pyo;Jeong, Ju-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.2
    • /
    • pp.1-8
    • /
    • 2009
  • We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

A Design of Pipelined Analog-to-Digital Converter with Multi SHA Structure (Multi SHA 구조의 파이프라인 아날로그-디지털 변환기 설계)

  • Lee, Seung-Woo;Ra, Yoo-Chan;Shin, Hong-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.2A
    • /
    • pp.114-121
    • /
    • 2005
  • In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

A Design of ADC with Multi SHA Structure which for High Data Communication (고속 데이터 통신을 위한 다중Multi SHA구조를 갖는 ADC설계)

  • Kim, Sun-Youb
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.11 no.9
    • /
    • pp.1709-1716
    • /
    • 2007
  • In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

A 6-b 400 MSPS CMOS folding and interpolating ADC

  • 한상찬;김수원
    • Proceedings of the IEEK Conference
    • /
    • 1998.10a
    • /
    • pp.691-694
    • /
    • 1998
  • This paper describes a 6-b 400 MSPS CMOS folding and interpolating(F&I) ADC. To overcome the delay difference of an MSB part and an LSB part in a typical F&I ADC the ADC is composed of only one LSB part and to alleviate the offset voltage of comparators in the LSB part preamplifiers are used in front of the comparators. This paper analyzes a folder and presents a design procedure of the folder. The ADC has the DNL of 0.3 LSB and the INL of 0.6 LSB and consumes the power of 120mW $$ 3 V. The ADC is designed in a 0.6 $\mu\textrm{m}$ CMOS process.

  • PDF

SCTP Performance Analysis based on ROHC

  • Shinn, Byung-Cheol;Feng, Bai
    • Journal of information and communication convergence engineering
    • /
    • v.5 no.4
    • /
    • pp.305-310
    • /
    • 2007
  • In this paper, an analysis has been done on the performance of SCTP header compression by using Robust Reader Compression (ROHC)[1] method. And it is assumed that the operating mode for ROHC is unidirectional mode (U-Mode) and the possible states are IR and SO states. The throughput of SCTP packets in wireless link and the impact of size of W-LSB encoding window on throughput are discussed.

Design of 8bit current steering DAC for stimulating neuron signal (뉴런 신호 자극을 위한 8비트 전류 구동형 DAC)

  • Park, J.H.;Shi, D.;Yoon, K.S.
    • Journal of rehabilitation welfare engineering & assistive technology
    • /
    • v.7 no.2
    • /
    • pp.13-18
    • /
    • 2013
  • In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

  • PDF

Design of The 10bit 80MHz CMOS D/A Converter with Switching Noise Reduction Method (스위칭 잡음 감소기법을 이용한 10비트 80MHz CMOS D/A 변환기 설계)

  • Hwang, Jung-Jin;Seon, Jong-Kug;Park, Li-Min;Yoon, Kwang-Sub
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.6
    • /
    • pp.35-42
    • /
    • 2010
  • This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

Pipelined A/D Converter with Multiple S/H Stage Structure (여러개의 S/H단 구조를 가지는 파이프라인 A/D변환기)

  • Cho Seong-Ik
    • The Transactions of the Korean Institute of Electrical Engineers D
    • /
    • v.54 no.3
    • /
    • pp.186-190
    • /
    • 2005
  • In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.