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A Design of Pipelined Analog-to-Digital Converter with Multi SHA Structure  

Lee, Seung-Woo (원광대학교 전자공학과)
Ra, Yoo-Chan (남서울대학교 전자정보통신공학부)
Shin, Hong-Kyu (원광대학교 전자공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.2A, 2005 , pp. 114-121 More about this Journal
Abstract
In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.
Keywords
Pipelined ADC; multi SHA; VDSL;
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