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Design of High Speed Pipelined ADC for System-on-Panel Applications  

Hong, Moon-Pyo (Department of Electronics Eng., Suwon University)
Jeong, Ju-Young (Department of Electronics Eng., Suwon University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.2, 2009 , pp. 1-8 More about this Journal
Abstract
We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.
Keywords
ADC; folding; pipeline; system-on-panel; display; circuit; converter;
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