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Design of The 10bit 80MHz CMOS D/A Converter with Switching Noise Reduction Method  

Hwang, Jung-Jin (Dep of Electronics Engineering, Inha University)
Seon, Jong-Kug (LG Industrial Systems)
Park, Li-Min (Dep of Electronics Engineering, Inha University)
Yoon, Kwang-Sub (Dep of Electronics Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.6, 2010 , pp. 35-42 More about this Journal
Abstract
This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.
Keywords
CMOS; Frequency detector circuit; Voltage level decrease circuit; DAC;
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