• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2003.10a
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• pp.101-106
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• 2003

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole quality is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene Terephthalate) one. In this paper we found the correlation between hole quality and process condition such as ceramic thickness, and tool size. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.190-192
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• 2006

The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.11
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• pp.2038-2042
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• 2010

In this paper, we confirmed the thermal & optical properties for improving the heat transfer coefficient by changing the via hole size and in FR4 PCB with the same area. Osram 1W power LED Package (Golden Dragon) was used and the K-factor which is relative constant between LED junction temperature and forward bias was measured with power source meter(KEITHLEY 2430) to measure the thermal resistance from PCB configuration. As results, thermal resistance in metal PCB came out to the lowest as $26 [^{\circ}C/W]$ and thermal resistance in FR4 PCB without via-holes emerged as the highest as $69 [^{\circ}C/W]$. However thermal resistance of FR4 PCB could have decreased until $32[^{\circ}C/W]$ in 0.6 mm by using the via hole. Also, the luminous flux could have improved, too.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.934-937
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• 1999

MMIC 제작을 위한 단일 반도체 공정으로써 PECVD를 이용한 Si₃N₄의 증착, RIE를 이용한 CaAs via-hole건식식각, 그리고 airbridge 공정조건을 위한 실험 및 분석 작업을 수행하였다. Si₃N₄의 증착 실험에서는 굴절률이 2인 조건을, GaAs via-hole 식각 실험에서는 최적화된 thru-via의 모양과 식각률을 갖는 조건을, airbridge 실험에서는 polyimide coating 및 건식 식각 조건과 금 도금 및 습식 식각의 최적 조건들을 찾아내었다.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1272-1278
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• 2009

The cancellation method of P/G(power/ground) plane resonances which are generated between the power plane and the ground plane in a 4-layer PCB(Printed Circuit Boards) with a via-hole for the improvement of the RE(Radiated Emission) characteristic is presented. The validity of the proposed method was confirmed from simulation and measurement of performances of signal transmission characteristic, intensities of edge-radiation and radiated emission of PCB with a via-hole.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.528-529
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• 2008

A new concept based on sample current measurements for detecting of via-hole defects on wafer has been performed by low energy electron beam microcolumn. The microcolumn has been operated at a low voltage of 290 eV with total emission current of 400 nA, and a sample current of 6 nA. The test sample was fabricated with SiO2 layer of 300 nm thickness on a piece of a silicon substrate. Preliminary results of both sample current method and secondary electron method show microcolumn and its control can be useful technology for detecting of via-hole defects on wafer.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.57-63
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• 2010

The efficiency of LED package is increasing by applying the high power, and a existing lighting is changing as the LED lighting. However, many problems have appeared by heat. Therefore, in order to solve thermal problems, LED lighting is designing in several ways, but the advantages of LED lighting is fading due to increase the prices and volumes. In this study, we try to improve the thermal performance by formation of via holes. The junction temperature and thermal resistance in the FR4-PCB with via-holes of 0.6[mm] was excellent in experiment and FR4-PCB with Via-holes of 0.6[mm] was excellent in simulation without solder. Further, the thermal resistance and the optical properties can be improved through a formation of via-holes.