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http://dx.doi.org/10.5369/JSST.2013.22.2.130

Low Cost Via-Hole Filling Process Using Powder and Solder  

Hong, Pyo-Hwan (School of Electronics Engineering, Kyungpook National University)
Kong, Dae-Young (School of Electronics Engineering, Kyungpook National University)
Nam, Jae-Woo (School of Electronics Engineering, Kyungpook National University)
Lee, Jong-Hyun (School of Electronics Engineering, Kyungpook National University)
Cho, Chan-Seob (School of Electrical Engineering, Kyungpook National University)
Kim, Bonghwan (Department of Electronics Engineering, Catholic University of Daegu)
Publication Information
Journal of Sensor Science and Technology / v.22, no.2, 2013 , pp. 130-135 More about this Journal
Abstract
This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.
Keywords
Filling; Powder; Soldering; TSV; Via hole;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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