• ETRI Journal
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• v.33 no.1
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.5
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• pp.95-104
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• 2003

The material properties of rubber was determined by the experiments of uniaxial tension, uniaxial compression, planer tension, equi-biaxial tension and volumetric compression. In compression test, it is difficult to obtain the pure state of compression stress and strain due to friction force between the specimen and compression platen. In this study, the stress and strain data from the equi-biaxial tension test were converted to compression stress and strain and compared to a pure state of simple compression data when friction was zero. The compression test device with the tapered platen was proposed to overcome the effect of friction. It was fumed out that the relationship of the stress and strain using the tapered platen was in close agreement with the pure compressive state.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.6
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• pp.515-520
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• 2004

Core-based system-on-a-chip (SoC) designs present a number of test challenges. Two major problems that are becoming increasingly important are long application time during manufacturing test and high volume of test data. Highly efficient compression techniques have been proposed to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. This paper proposes a new test data compression technique for SoC testing. In the proposed technique, compression is achieved by partitioning the test vector set and removing repeating segment. This process has $O(n^{-2})$ time complexity for compression with a simple hardware decoding circuitry. It is shown that the efficiency of the proposed compression technique is comparable with sophisticated software compression techniques with the advantage of easy and fast decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.87-95
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• 2004

This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.397-403
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• 2015

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.425-430
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• 2003

The material properties of rubber was determined by the experiments of uniaxial tension, uniaxial compression, planer tension, equi-biaxial tension and volumetric compression. In compression test, it is difficult to obtain the pure state of compression stress and strain due to friction force between the specimen and compression platen. In this study, the stress and strain data from the equi-biaxial tension test were converted to compression stress and strain and compared to a perfect state of simple compression data when friction was zero. The compression test device with the tapered platen was proposed to overcome the effect of friction. It was turned out that the relationship of the stress and strain using the tapered platen was in close agreement with the pure compressive state.

• Journal of the Korea institute for structural maintenance and inspection
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• v.6 no.1
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• pp.223-231
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• 2002

The pilot tests for the development of biaxial failure envelope of high strength concrete of reactor containments were performed. To apply biaxial loads to concrete, the plate specimens were used. The technical difficulties encountered on the development of a suitable biaxial test setup were discussed. To decide the optimum thickness of plate specimen, the nonlinear finite element analyses using ABAQUS were performed for a 1/8 model of cylindrical specimen(${\Phi}150{\times}300$) and four 1/4 models of plate Specimens ($200{\times}200{\times}T$(=30, 50, 60, 70)mm) under uniaxial compression. Analytical values and test data of relative strength ratio between those specimens with different geometric shapes were also compared. The various test data were obtained under uniaxial compression, uniaxial tension, and biaxial compression and then the stress-strain responses were plotted. The test data indicated that the strength of concrete under biaxial compression, $f_1/f_2=-1/-1$, is 15 percent larger than that under uniaxial compression and the poisson's ratio of concrete is 0.16. Teflon pads employed to eliminate friction between test specimen and loading platens showed an excellent effect under biaxial compression.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.104-110
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• 2006

The huge test data volume, test time and power consumption are major problems in system-on-a-chip testing. To tackle those problems, we propose a new test data compression technique. Initially, don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption, and then, the fully specified low-power test data is transformed to improve compression efficiency by neighboring bit-wise exclusive-or (NB-XOR) scheme. Finally, the transformed test set is compressed to reduce both the test equipment storage requirements and test application time.