1 |
Marinissen, E.J.: 'The role of test protocols in automated test generation for embedded-corebased system ICs', J. Electron. Test., Theory Appl., vol.18, no.4, pp. 435-454, 2002.
DOI
ScienceOn
|
2 |
J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, "Embedded deterministic test," IEEE Trans. CAD, vol. 23, no.5, pp. 776-792, 2004.
DOI
ScienceOn
|
3 |
V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test wrapper and test access mechanism cooptimization for system-on-chip," J. Electron. Test., Theory Appl., vol.18, no.2, pp. 213-230, 2002.
DOI
ScienceOn
|
4 |
G. Giles, J. Wang, A. Sehgal, K. J. Balakrishnan, and J. Wingfield, "Test access mechanism for multiple identical cores," Proc ITC, paper 2.3, 2008.
|
5 |
M. Agrawal, K. Chakrabarty, "Test-time optimization in NOC-based manycore SOCs using multicast routing," Proc. of IEEE VLSI Test Symposium, pp.276-281, 2014.
|
6 |
T. Han, I. Choi, H. Oh, and S. Kang, "A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System," Proc. of Asian Test Symposium, pp.81-86, 2014
|
7 |
C. Yao, K.K.Saluja, P. Ramanathan, "Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, no. 2 , pp. 317- 322, 2011.
DOI
ScienceOn
|
8 |
R. Michael and C. Krishnendu, "Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs," IEEE Trans. on Computers, vol. 63, no.3, pp. 691-702, 2014.
DOI
ScienceOn
|
9 |
Q. Xu and N. Nicolici, "Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores," Proc. ITC, pp. 1196-1202, 2004.
|
10 |
S. K. Goel, E. J. Marinissen, A. Sehgal, and K. Chakrabarty "Testing of SoCs with hierarchical cores: common fallacies, test access optimization, and test scheduling," IEEE Trans. Comput., vol. 58, no.3, pp. 409-423, 2009.
DOI
ScienceOn
|
11 |
Q. Xu and N. Nicolici, "Resource-Constrained System-on a-Chip Test: A Survey", IEE Proc. Computers & Digital Techniques, vol. 152, no. 1, pp. 67-81, 2005.
|
12 |
Z. Wang, K. Chakrabarty, and S. Wang, "Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip," IEEE Trans. CAD, vol. 28, no.8, pp. 1251 -1263, 2009.
DOI
ScienceOn
|
13 |
M. Tehranipoor, M. Nourani, and K. Chakrabarty, "Nine-Coded Compression Techniques for Testing Embedded Cores in SoCs," IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 719-722, 2005.
DOI
ScienceOn
|
14 |
Z. Wang., K. Chakrabarty, S. Wang, "SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling," Design, Automation &Test in Europe Conference & Exhibition, pp.1-6, 2007.
|
15 |
V. Iyengar, and A. Chandra, "Unified SOC Test Approach based on Test Data Compression and TAM Design," IEE Proc. Computers & Digital Techniques, vol.152, no. 1, pp. 82-88, 2005.
|
16 |
P.T. Gonciari, P. Rosinger, and B.M. Al-Hashimi, "Compression Considerations in Test Access Mechanism Design," IEE Proc. Computers & Digital Techniques, vol.152, no. 1, pp. 89-96, 2005.
DOI
ScienceOn
|
17 |
A. B. Kinsman and N. Nicolici, "Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels," Proc. ETS, pp. 196-201, 2005.
|
18 |
Tieqiao Liu, Yingbo Zhou, Yi Liu and Shuo Cai, "Harzard-Based ATPG for Improving Delay Test Quality," Journal of Electronic Testing, vol.31, no.1, pp. 27-34, 2015.
DOI
|
19 |
J. Janicki, J. Tyszer, G. Mrugulski, and J. Rajski, "Bandwidth-Aware Test Compression Logic for SoC Designs," Proc. of European Test Symp., 2012
|
20 |
J. Janicki, J. Tyszer, W.-T. Cheng, Y. Huang, M. Kassab, N. Mukherjee, J. Rajski, Y. Dong, G. Giles, "EDT Bandwidth Management - Practical Scenarios for Large SoC Designs," Proc. of International Test Conference, Paper 4.3, 2013.
|
21 |
M. Trawka, G. Mrugalski, N. Mukherjee, A. Pogiel, J. Rajski, J. Janicki, J. Tyszer, "High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs," Proc. of Asian Test Symposium, pp.74-80, 2014.
|
22 |
S.S. Muthyala, N.A Touba, "SOC Test Compression Scheme Using Sequential Linear Decompressors with Retained Free Variables," Proc. of VLSI Test Symposium, pp.31-36, 2013.
|