• 제목/요약/키워드: Strained layer

검색결과 66건 처리시간 0.022초

Theoretical Study of Electron Mobility in Double-Gate Field Effect Transistors with Multilayer (strained-)Si/SiGe Channel

  • Walczak, Jakub;Majkusiak, Bogdan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제8권3호
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    • pp.264-275
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    • 2008
  • Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

고농도의 Ge 함량을 가진 Biaxially Strained SiGe/Si Channel Structure의 정공 이동도 특성 (Hole Mobility Characteristics of Biaxially Strained SiGe/Si Channel Structure with High Ge Content)

  • 정종완
    • 한국전기전자재료학회논문지
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    • 제21권1호
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    • pp.44-48
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    • 2008
  • Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

Strained Si/Relaxed SiGe/SiO2/Si 구조 FD n-MOSFET의 전자이동에 Ge mole fraction과 strained Si 층 두께가 미치는 영향 (Effect of Ge mole fraction and Strained Si Thickness on Electron Mobility of FD n-MOSFET Fabricated on Strained Si/Relaxed SiGe/SiO2/Si)

  • 백승혁;심태헌;문준석;차원준;박재근
    • 대한전자공학회논문지SD
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    • 제41권10호
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    • pp.1-7
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    • 2004
  • SOI 구조에서 형성된 MOS 트랜지스터의 장점과 strained Si에서 전자의 이동도가 향상되는 효과를 동시에 고려하기 위해 buried oxide(BOX)층과 Top Si층 사이에 Ge을 삽입하여 strained Si/relaxed SiGe/SiO₂Si 구조를 형성하고 strained Si fully depletion(FD) n-MOSFET를 제작하였다. 상부 strained Si층과 하부 SiGe층의 두께의 합을 12.8nm로 고정하고 상부 strained Si 층의 두께에 변화를 주어 두께의 변화가 electron mobility에 미치는 영향을 분석하였다. Strained Si/relaxed SiGe/SiO2/Si (strained Si/SGOI) 구조위의 FD n-MOSFET의 전자 이동도는 Si/SiO₂/Si (SOI) 구조위의 FD n-MOSFET 에 비해 30-80% 항상되었다. 상부 strained Si 층과 하부 SiGe 층의 두께의 합을 12.8nm 로 고정한 shrined Si/SGOI 구조 FD n-MOSFET에서 상부층 strained Si층의 두께가 감소하면 하부층 SiGe 층 두께 증가로 인한 Ge mole fraction이 증가함에 의해 inter-valley scattering 이 감소함에도 불구하고 n-channel 층의 전자이동도가 감소하였다. 이는 strained Si층의 두께가 감소할수록 2-fold valley에 있는 전자가 n-channel 층에 더욱더 confinement 되어 intra-valley phonon scattering 이 증가하여 전자 이동도가 감소함이 이론적으로 확인되었다.

초고속 구동을 위한 Ultra-thin Strained SGOI n-MOS 트랜지스터 제작 (High Performance nFET Operation of Strained-SOI MOSFETs Using Ultra-thin Strained Si/SiGe on Insulator(SGOI) Substrate)

  • 맹성렬;조원주;오지훈;임기주;장문규;박재근;심태헌;박경완;이성재
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1065-1068
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    • 2003
  • For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

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소성인장변형 몇 아연도금된 Fe-Mn-C계 TWIP 강의 전기화학적 수소투과거동 (Electrochemical Hydrogen Permeation Behaviors of Pre-Strained Fe-Mn-C TWIP Steel With or Without Zn Coating)

  • 김성진
    • Corrosion Science and Technology
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    • 제22권4호
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    • pp.297-303
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    • 2023
  • This study aimed to evaluate hydrogen permeation behaviors of pre-strained twinning-induced plasticity steel with or without Zn coating using electrochemical permeation technique. In contrast to un-strained and 30% strained samples, permeation current density was measured in the 60% strained sample. Tensile pre-straining at 60% involved microstructural modifications, including a high level of dislocation density and stacking fault with a semi-coherent twin boundary, which might provide a high diffusion path for hydrogen atoms. However, reproducibility of measurements of hydrogen permeation current was low due to non-uniform deformation and localized stress concentration. On the other hand, the permeation current was not measured in pre-strained TWIP steel with Zn coating. Instead, numerous blisters with some cracks were observed on the surface of the coating layer. In locally damaged Zn coating under tensile straining, hydrogen atoms could relatively easily permeate through the coating layer. However, they were trapped at the interface between the coating layer and the substrate, which might delay hydrogen penetration into the steel substrate.

Strained Si를 만들기 위한 SiGe layer 형성에 temperature, $GeH_4$ gas pre-flow, gas ratio가 미치는 영향 (Effect of temperature, $GeH_4$ gas pre-flow, gas ratio on formation of SiGe layer for strained Si)

  • 안상준;이곤섭;박재근
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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    • pp.60-60
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    • 2003
  • 디자인 룰에 의해 Gate Length 가 100nm 이하로 줄어듦에 따라 Gate delay 감소와 Switch speed 향상을 위해 보다 더 큰 drive current 를 요구하게 되었다. 본 연구는 dirve current 를 증가시키기 위해 고안된 Strained Si substrate 를 만들기 위한 SiGe layer 성장에 관한 연구이다. SiGe layer를 성장시킬 때 SiH$_4$ gas와 GeH$_4$ gas를 furnace에 flow시켜 Chemical 반응에 의해 Si Substrate를 성장시키는 LPCVD(low pressure chemical vapor depositio)법을 사용하였고 SIMS와 nanospec을 이용하여 박막 두께 및 Ge concentration을 측정하였고, AFM으로 surface의 roughness를 측정하였다. 본 연구에서 우리는 10,20,30,40%의 Ge concentration을 갖는 10nm 이하의 SiGe layer를 얻기 위하여 l0nm 이하의 fixed 된 두께로 SiGe layer를 성장시킬 때 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$의 gas ratio를 변화시켜 성장시킨 후 Ge 의 concentration과 실제 형성된 두께를 측정하였고, SiGe의 mole fraction의 변화에 따른 surface의 roughness 를 측정하였다. 그 결과 10 nm의 두께에서 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$ 의 gas ratio의 변화와 Ge concentration 과의 의존성을 확인 할 수 있었고, SiGe 의 mole traction이 증가하였을 때 surfcace의 roughness 가 증가함을 알 수 있었다. 이 연구 결과는 strained Si 가 가지고 있는 strained Si 내에서 n-FET 와 P-FET사이의 불균형에 대한 해결과 좀 더 발전된 형태인 fully Depleted Strained Si 제작에 기여할 것으로 보인다.

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Strained-SiGe Complementary MOSFETs Adopting Different Thicknesses of Silicon Cap Layers for Low Power and High Performance Applications

  • Mheen, Bong-Ki;Song, Young-Joo;Kang, Jin-Young;Hong, Song-Cheol
    • ETRI Journal
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    • 제27권4호
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    • pp.439-445
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    • 2005
  • We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

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단일채널 Strained Si/SiGe 구조와 이중채널 Strained Si/SiGe 구조의 이동도 특성 비교 (Comparison of Hole Mobility Characteristics of Single Channel and Dual Channel Si/SiGe Structure)

  • 정종완
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.113-114
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    • 2007
  • Hole mobility characteristics of single surface channel and dual channel Si/SiGe structure are compared, where the former one consists of a relaxed SiGe buffer layer and a tensile strained Si layer on top, and for dual channel structure a compressively strained SiGe layer is inserted between them. Due to the difference of hole mobility enhancement factors of layers between them, hole mobility characteristics with respect to the Si cap thickness shows the opposite tend. Hole mobility increases with thicker Si cap for single channel structure, whereas it decreases with thicker Si cap for dual channel structure.

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Strained SGOI n-MOSFET에서의 phonon-limited전자이동도의 Si두께 의존성 (Dependency of Phonon-limited Electron Mobility on Si Thickness in Strained SGOI (Silicon Germanium on Insulator) n-MOSFET)

  • 심태헌;박재근
    • 대한전자공학회논문지SD
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    • 제42권9호
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    • pp.9-18
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    • 2005
  • 60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다

Improvement of Carrier Mobility on Silicon-Germanium on Insulator MOSFET Devices with a Strained-Si Layer

  • Cho, Won-Ju;Koo, Hyun-Mo;Lee, Woo-Hyun;Koo, Sang-Mo;Chung, Hong-Bay
    • 한국전기전자재료학회논문지
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    • 제20권5호
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    • pp.399-402
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    • 2007
  • The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.