• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.691-694
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as charge distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.467-468
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• Journal of Sensor Science and Technology
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• v.30 no.6
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.169-169
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• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.678-686
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• 2001

Origins for the transconductance dispersion and the gate leakage current in a GaAs metal semiconductor field effect transistor were found using capacitance deep-level transient spectroscopy (DLTS) measurements. In DLTS spectra, we observed two surface states with thermal activation energies of 0.65 $\times$ 0.07 eV and 0.88 $\times$ 0.04 eV and an electron trap EL2 with thermal activation energy of 0.84 $\times$ 0.01 eV. Transconductance was decreased in the frequency range of 5.5 Hz ~ 300 Hz. The transition frequency shifted to higher frequencies with the increase of temperature and the activation energy for the change of the transition frequency was determined to be 0.66 $\times$ 0.02 eV. From the measurements of the gate leakage current as a function of the device temperature, the forward and reverse currents are coincident with each other below gate voltages lower than 0.15 V, namely Ohmic behavior between gate and source/drain electrodes. The activation energy for the conductance of electrons on the surface of MESFET was 0.63 $\times$ 0.01 eV. Comparing activation energies obtained by different measurements, we found surface states H1 caused the transconductance dispersion and the fate leakage current.

• ETRI Journal
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• v.42 no.4
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.223-229
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• 2017

This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.289.2-289.2
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• 2016

In-Ga-Zn-O(IGZO) receive great attention as a channel material for thin film transistors(TFTs) as next-generation display panel backplanes due to its superior electrical and physical properties such as a high mobility, low off-current, high sub-threshold slope, flexibility, and optical transparency. For the purpose of fabricating high performance IGZO TFTs, a thermal recovery process above a temperature of $300^{\circ}C$ is required for recovery or rearrangement of the ionic bonding structure. However diffused metal atoms from source/drain(S/D) electrodes increase the channel conductivity through the oxidation of diffused atoms and reduction of $In_2O_3$ during the thermal recovery process. Threshold voltage ($V_{TH}$) shift, one of the electrical instability, restricts actual applications of IGZO TFTs. Therefore, additional investigation of the electrical stability of IGZO TFTs is required. In this paper, we demonstrate the effect of Ti diffusion and modulation of interface traps by carrying out an annealing process on IGZO. In order to investigate the effect of diffused Ti atoms from the S/D electrode, we use secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy, HSC chemistry simulation, and electrical measurements. By thermal annealing process, we demonstrate VTH shift as a function of the channel length and the gate stress. Furthermore, we enhance the electrical stability of the IGZO TFTs through a second thermal annealing process performed at temperature $50^{\circ}C$ lower than the first annealing step to diffuse Ti atoms in the lateral direction with minimal effects on the channel conductivity.

• The Journal of the Convergence on Culture Technology
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• v.4 no.3
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• pp.287-291
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• 2018

The CNTFET, which is attracting attention as a next-generation semiconductor device, can obtain ballistic or near-ballistic transport at a lower voltage than that of conventional MOSFETs by depositing CNTs between the source and drain of the device. In order to increase the performance of the CNTFET, a large number of CNTs must be deposited at a high density in the CNTFET. Thus, various manufacturing processes to increase the density of the CNTs have been developed. Recently, the Directional Shrinking Transfer Method was developed and showed that the current density of the CNTFET device could be increased up to 150 uA/um. So, this method enhances the possibility of implementing a CNTFET-based integrated circuit. In this paper, we will discuss how to evaluate the performance of the CNTFET device compared to a MOSFET at the circuit level when the CNTFET is fabricated by the Directional Shrinkage Transfer Method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.12-16
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• 2011

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.