• Title/Summary/Keyword: SoC 테스트

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Integration of SoC Test and Verification Using Embedded Processor and Reconfigurable Architecture (임베디드 프로세서와 재구성 가능한 구조를 이용한 SoC 테스트와 검증의 통합)

  • Kim Nam-Sub;Cho Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.7 s.349
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    • pp.38-49
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    • 2006
  • In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

Development of Simple Reconfigurable Access Mechanism for SoC Testing (재구성 가능한 시스템 칩 테스트 제어기술의 개발)

  • 김태식;민병우;박성주
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.9-16
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    • 2004
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

SA-Based Test Scheduling to Reduce the Test Time of NoC-Based SoCS (SA 기법 응용 NoC 기반 SoC 테스트 시간 감소 방법)

  • Ahn, Jin-Ho;Kim, Hong-Sik;Kim, Hyun-Jin;Park, Young-Ho;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.93-100
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    • 2008
  • In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

A Design of Flag Based Wrapped Core Linking Module for Hierarchical SoC Test Access (계층적 SoC테스트 접근을 위한 플래그 기반 코아 연결 모듈의 설계)

  • 송재훈;박성주;전창호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.1
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    • pp.52-60
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    • 2003
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

Test Scheduling Algorithm of System-on-a-Chip Using Extended Tree Growing Graph (확장 나무성장 그래프를 이용한 시스템 온 칩의 테스트 스케줄링 알고리듬)

  • 박진성;이재민
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.93-100
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    • 2004
  • Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.

A Parallel Structure of SRAMs in embedded DRAMs for Testability (테스트 용이화를 위한 임베디드 DRAM 내 SRAM의 병열 구조)

  • Gook, In-Sung;Lee, Jae-Min
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.3 no.3
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    • pp.3-7
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    • 2010
  • As the distance between signal lines in memories of high density ICs like SoCs decreases rapidly, failure occurs more frequently and effective memory test techniques are needed. In this paper, a new SRAM structure is proposed to decrease test complexity and test time for embedded DRAMs. In the presented technique, because memory test can be handled as a single port testing and read-write operation is possible at dual port without high complexity, test time can be much reduced.

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A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access (계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계)

  • Yi Hyun-Bean;Park Sung-Ju
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.3
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    • pp.156-162
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    • 2003
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

An Efficient SoC Test Architecture for Testing Various Cores in Parallel (다양한 코어의 병렬 테스트를 지원하는 효과적인 SOC 테스트 구조)

  • Kim, Hyun-Sik;Kim, Yong-Joon;Park, Hyun-Tae;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.140-150
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    • 2006
  • In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

Design of Enhanced IEEE 1500 Wrapper Cell and Interface Logic For Transition Delay Fault Test (천이 지연 고장 테스트를 위한 개선된 IEEE 1500 래퍼 셀 및 인터페이스 회로 설계)

  • Kim, Ki-Tae;Yi, Hyun-Bean;Kim, Jin-Kyu;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.109-118
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    • 2007
  • As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

Exploiting an On/off-Chip Bus Bridge for an Efficiently Testable SoC (효율적인 SoC 테스트를 위한 온/오프-칩 버스 브리지 활용기술에 대한 연구)

  • Song, Jae-Hoon;Han, Ju-Hee;Kim, Byeong-Jin;Jeong, Hye-Ran;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.105-116
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    • 2008
  • Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.