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A Design of Flag Based Wrapped Core Linking Module for Hierarchical SoC Test Access  

송재훈 (한양대학교 전자컴퓨터공학부)
박성주 (한양대학교 전자컴퓨터공학부)
전창호 (한양대학교 전자컴퓨터공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.1, 2003 , pp. 52-60 More about this Journal
Abstract
For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.
Keywords
IEEE 1149.1; P1500;
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