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SA-Based Test Scheduling to Reduce the Test Time of NoC-Based SoCS  

Ahn, Jin-Ho (Hoseo Univ., Electronic Engineering)
Kim, Hong-Sik (Yonsei Univ., Electrical&Electronic Engineering)
Kim, Hyun-Jin (Yonsei Univ., Electrical&Electronic Engineering)
Park, Young-Ho (ETRI, Network Tech. Lab., NoC Tech. Team)
Kang, Sung-Ho (Yonsei Univ., Electrical&Electronic Engineering)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 93-100 More about this Journal
Abstract
In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.
Keywords
NoC; Rectangle Packing; Simulated Annealing;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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