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Test Scheduling Algorithm of System-on-a-Chip Using Extended Tree Growing Graph  

박진성 (주식회사 텔리즘 통신기술연구소)
이재민 (관동대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.3, 2004 , pp. 93-100 More about this Journal
Abstract
Test scheduling of SoC (System-on-a-chip) is very important because it is one of the prime methods to minimize the testing time under limited power consumption of SoC. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoC is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position in test space to minimize the idling test time of test resources. The efficiency of proposed algorithm is confirmed by experiment using ITC02 benchmarks.
Keywords
System-on-a-Chip; Test Scheduling; Tree Growing Graph; Test Modeling;
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