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Design of Enhanced IEEE 1500 Wrapper Cell and Interface Logic For Transition Delay Fault Test  

Kim, Ki-Tae (Dept. of Computer Science & Engineering, Hanyang University)
Yi, Hyun-Bean (Dept. of Computer Science & Engineering, Hanyang University)
Kim, Jin-Kyu (Dept. of Computer Science & Engineering, Hanyang University)
Park, Sung-Ju (Dept. of Electronical Engineering Computer Science, Hanyang Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.11, 2007 , pp. 109-118 More about this Journal
Abstract
As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.
Keywords
Transition delay fault; SoC; IEEE 1500; IEEE 1149.1; wrapper;
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