• Title/Summary/Keyword: Sn-TSV

Search Result 17, Processing Time 0.04 seconds

Manufacture of TSVs (Through-Silicon Vias) based on Single-Walled Nanotubes (SWNTs)/Sn Composite at Low Temperature (저온 공정을 통해 제작이 가능한 Sn/SWNT 혼합 파우더 기반의 TSV구조 개발)

  • Jung, Dong Geon;Jung, Daewoong;Kong, Seong Ho
    • Journal of Sensor Science and Technology
    • /
    • v.28 no.2
    • /
    • pp.127-132
    • /
    • 2019

  • In this study, the fabrication of through-silicon vias (TSVs) filled with SWNTs/Sn by utilizing surface/bulk micromachining and MEMS technologies is proposed. Tin (Sn) and single-walled nanotube (SWNT) powders are used as TSV interconnector materials in the development of a novel TSV at low temperature. The measured resistance of a TSV filled with SWNT/Sn powder is considerably reduced by increasing the fraction of Sn and is lower than that of a TSV filled with only Sn. This is because of a decrease in the surface scattering of electrons along with an increase in the grain size of sintered SWNTs/Sn. The proposed method is conducted at low temperatures (< $400^{\circ}C$) due to the low melting temperature of Sn; hence, the proposed TSVs filled with SWNTs/Sn can be utilized in CMOS based applications.

  • https://doi.org/10.5369/JSST.2019.28.2.127 인용 PDF KSCI HTML

Development of SiC Composite Solder with Low CTE as Filling Material for Molten Metal TSV Filling (용융 금속 TSV 충전을 위한 저열팽창계수 SiC 복합 충전 솔더의 개발)

  • Ko, Young-Ki;Ko, Yong-Ho;Bang, Jung-Hwan;Lee, Chang-Woo
    • Journal of Welding and Joining
    • /
    • v.32 no.3
    • /
    • pp.68-73
    • /
    • 2014

  • Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a $14.8ppm/^{\circ}C$ and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

  • https://doi.org/10.5781/JWJ.2014.32.3.68 인용 PDF KSCI

Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages (칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정)

  • Kim, Min-Young;Oh, Taek-Soo;Oh, Tae-Sung
    • Korean Journal of Metals and Materials
    • /
    • v.48 no.6
    • /
    • pp.557-564
    • /
    • 2010

  • Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

  • https://doi.org/10.3365/KJMM.2010.48.06.557 인용 KSCI