대한금속재료학회지 (Korean Journal of Metals and Materials)

  • 제48권6호
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  • Pages.557-564
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  • 2010
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  • 1738-8228(pISSN)
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  • 2288-8241(eISSN)
대한금속재료학회 (The Korean Institute of Metals and Materials)
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칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정

Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages

  • 김민영 (홍익대학교 신소재공학과) ;
  • 오택수 (홍익대학교 신소재공학과) ;
  • 오태성 (홍익대학교 신소재공학과)
  • Kim, Min-Young (Materials Science and Engineering, Hongik University) ;
  • Oh, Taek-Soo (Materials Science and Engineering, Hongik University) ;
  • Oh, Tae-Sung (Materials Science and Engineering, Hongik University)
  • 투고 : 2009.10.26
  • 발행 : 2010.06.22
⟨ 이전 논문 다음 논문 ⟩

초록

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

키워드

과제정보

연구 과제 주관 기관 : 전자패키지재료연구센터

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