References
- J. H. Jun, I. R Kim, M. Mayer, Y. N. Zhou, S. B. Jung and J. P. Jung : A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packa- ging, Materials Transactions, 2010, 1887- 1892
- M. Tomisaka, M. Hoshino, H. Yonemura and K. Takahashi : Copper Electroplating Study for Through Silicon Chip Electrode of Three-dimensional Chip Stacking, Denso Tech. Rev. Vol. 6 (2001), 78-84
- S. J. Hong, Y. W. Lee, K. S. Kim, K. J. Lee, J. O. Kim, J. H. Park, J. P. Jung : Filling via hole in Si-wafer for 3 Dimensional Packaging, The Korean Welding and Joining Society Conference, 2006 (in Korean)
- B. S. Kang, S. M. Lee, J. S. Kwak, D. S. Yoon and H. K. Baik : The Effectiveness of Ta Prepared by Ion- Assisted Deposition as a Diffusion Barrier Between Copper and Silicon, J. Electrochem. Soc., 144 (1997), 1807- 1812 https://doi.org/10.1149/1.1837684
- M. S. Yoon : Introduction of TSV (Through Silicon Via) Technology, J. Microelectron. Packag. Soc, 16-1(2009), 1-6 (in Korean)
- S. J. Hong, S. C. Hong, W. J. Kim, and J. P. Jung : Copper Filling to TSV (Through-Si-Via) and Simplification of Bumping Process, Journal of the Microelectronics & Packaging Society, 17-3 (2010), 79-84 (in Korean)
- I. R. Kim, J, K, Park, Y. C. Chu, and J. P. Jung : High speed Cu Filling Into TSV by Pulse Current for 3 Dimensional Chip Stacking, J. Met. Mater., 48-7 (2010), 667-673 (in Korean)
- S. J. Hong, J. H. Jun, J. P. Jung, M. Mayer and Y. Norman Zhou : Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging, IEEE TRANS. ADV. PACK., in press(2010)
Cited by
- Various Cu Filling Methods of TSV for Three Dimensional Packaging vol.31, pp.3, 2013, https://doi.org/10.5781/KWJS.2013.31.3.11