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Manufacture of TSVs (Through-Silicon Vias) based on Single-Walled Nanotubes (SWNTs)/Sn Composite at Low Temperature

저온 공정을 통해 제작이 가능한 Sn/SWNT 혼합 파우더 기반의 TSV구조 개발

  • Jung, Dong Geon (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Jung, Daewoong (Aircraft System Technology Group, Korea Institute of Industrial Technology) ;
  • Kong, Seong Ho (School of Electronics Engineering, Kyungpook National Unversity)
  • 정동건 (경북대학교 전자공학부) ;
  • 정대웅 (한국생산기술연구원한국시스템기술그룹) ;
  • 공성호 (경북대학교 전자공학부)
  • Received : 2018.12.27
  • Accepted : 2019.03.27
  • Published : 2019.03.31

Abstract

In this study, the fabrication of through-silicon vias (TSVs) filled with SWNTs/Sn by utilizing surface/bulk micromachining and MEMS technologies is proposed. Tin (Sn) and single-walled nanotube (SWNT) powders are used as TSV interconnector materials in the development of a novel TSV at low temperature. The measured resistance of a TSV filled with SWNT/Sn powder is considerably reduced by increasing the fraction of Sn and is lower than that of a TSV filled with only Sn. This is because of a decrease in the surface scattering of electrons along with an increase in the grain size of sintered SWNTs/Sn. The proposed method is conducted at low temperatures (< $400^{\circ}C$) due to the low melting temperature of Sn; hence, the proposed TSVs filled with SWNTs/Sn can be utilized in CMOS based applications.

Keywords

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Fig. 1. Fabrication process of the proposed TSV structure

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Fig. 2. SEM images of TSVs filled with Al and Sn powder

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Fig. 3. Measured resistance of TSVs filled with Sn powder

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Fig. 4. SEM images of TSVs along with increasing SWNTs proportion

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Fig. 5. SEM images of TSVs along with increasing Sn powder proportion

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Fig. 6. Sinterned Sn/SWNT powder's grain size along with increasing Sn powder proportion

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Fig. 7. Measured resistance of TSVs along with increasing SWNT powder

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Fig. 8. Measured resistance of TSVs along with increasing Sn powder

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