• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• 대한금속재료학회지
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• 제50권8호
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• pp.613-618
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• 2012

We report on electrical and mechanical properties of silicon nitride ($SiN_x$) films deposited by a plasma enhanced chemical vapor deposition (PECVD) method at $200^{\circ}C$ from $SiH_4$ highly diluted in $N_2$. The films were also prepared from $SiH_4$ diluted in He for comparison. The $N_2$ dilution was also effective in improving adhesion of the $SiN_x$ films, fascilitating construction of thin film transistors (TFTs). Metal-insulator-semiconductor (MIS) and Metal-insulator-Metal (MIM) structures were used for capacitance-voltage (C-V) and current-voltage (I-V) measurements, respectively. The resistivity and breakdown field strength of the $SiN_x$ films from $N_2$-diluted $SiH_4$ were estimated to be $1{\times}10^{13}{\Omega}{\cdot}cm$, 7.4 MV/cm, respectively. The MIS device showed a hysteresis window and a flat band voltage shift of 3 V and 0.5 V, respectively. The TFTs fabricated by using these films showed a field-effect mobility of $0.16cm^2/Vs$, a threshold voltage of 3 V, a subthreshold slope of 1.2 V/dec, and an on/off ratio of > $10^6$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.47-51
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• 2000

A modified direct bonding technique employing a wet chemical deposition of $SiO_2$ film on a wafer surface to be bonded is proposed for the fabrication of Si-$SiO_2$-Si structures. Structural and electrical quality of the bonded wafers is studied. Satisfied insulating properties of interfacial $SiO_2$ layers are demonstrated. Elastic strain caused by surface morphology is investigated. The diminution of strain in the grooved structures is semi-quantitatively interpreted by a model considering the virtual defects distributed over the interfacial region.

• 센서학회지
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• 제7권1호
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• pp.73-82
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• 1998

실리콘 표면 미세가공에 있어서, 새로 개발된 HF 기상식각 공정은 미소구조체들을 띄우는데 매우 효과적임을 입증하였다. 무수 불화수소와 메탄올을 이용한 기상식각 시스템에 대한 기능 및 특성을 기술하였고, 실리콘 미세구조체룰 띄우기 위한 회생층 산화막들의 선택적 식각특성이 고찰되었다. 구조체층으로는 인이 주입된 다결정실리콘이나 SOI 기판의 단결정실리콘을 사용하였다. 회생층으로는 TEOS 산화막, 열산화막, 저온산화막을 사용하였다. 기존 습식식각과 비교해 볼 때, 공정에 기인된 고착현강이나 잔류물질이 없는 미세구조체를 성공적으로 제작하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• 한국재료학회지
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• 제16권10호
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• pp.652-655
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• 2006

A direct wafer bonding process necessary for GaAs-on-insulator (GOI) fabrication with high thermal annealing temperatures was studied by using PECVD oxides between gallium arsenide and silicon wafers. In order to apply some uniform pressure on initially-bonded wafer pairs, a graphite sample holder was used for wafer bonding. Also, a tool for measuring the tensile forces was fabricated to measure the wafer bonding strengths of both initially-bonded and thermally-annealed samples. GaAs/$SiO_2$/Si wafers with 0.5-$\mu$m-thick PECVD oxides were annealed from $100^{\circ}C\;to\;600^{\circ}C$. Maximum bonding strengths of about 84 N were obtained in the annealing temperature range of $400{\sim}500^{\circ}C$. The bonded wafers were not separated up to $600^{\circ}C$. As a result, the GOI wafers with high annealing temperatures were demonstrated for the first time.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.9-18
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• 2005

60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다

• 한국전기전자재료학회논문지
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• 제34권1호
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• pp.16-20
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• 2021

In this study, we tried finding new materials to improve the stain resistance properties of polymer insulating materials. Using the filtered vacuum arc source (FVAS) with a graphite target source, DLC thin films were deposited on silicon and polymer insulator substrates depending on their thickness to confirm the surface properties, physical properties, and structural properties of the thin films. Subsequently, the possibility of using a DLC thin film as a protective coating material for polymer insulators was confirmed. DLC thin films manufactured in accordance with the thickness of various thin films exhibited a very smooth and uniform surface. As the thin film thickness increased, the surface roughness value decreased and the contact angle value increased. In addition, the elastic modulus and hardness of the DLC thin film slightly increased, and the maximum values of elastic modulus and hardness were 214.5 GPa and 19.8 GPa, respectively. In addition, the DLC thin film showed a very low leakage current value, thereby exhibiting electrical insulation properties.