• Title/Summary/Keyword: Side gate

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Analysis of Electrical Characteristics for Double Gate MOSFET (Double Gate MOSFET의 전기적 특성 분석)

  • 김근호;김재홍;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.261-263
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    • 2002
  • CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

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A Study on Characteristics of Current-Voltage Relation by sizes for Double Gate MOSFET (DGMOSFET의 크기에 따른 전류-전압특성변화에 관한 연구)

  • Jung, Hak-Kee;Na, Young-Il;Lee, Jae-Hyung
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.884-886
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    • 2005
  • In this paper, we have investigated characteristics of current-voltage for double gate MOSFET with main gate and side gate. Investigated current-voltage characteristics of channel length changed len호 of channel from 1${\mu}$m to 3${\mu}$m. Also, compare and analyzed characteristics of changed of operation temperature changing current that is dignity. gate voltage could know 2V that is superior than device characteristics of current voltage characteristic in 77K acts in room temperature when approved.

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Dynamic characteristics for Double Gate MOSFET (더블게이트 MOSFET의 동적 특성)

  • Ko Suk-woong;Jung Hak-kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.8
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    • pp.1749-1753
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    • 2005
  • In this paper, we have investigated electrical characteristics by action temperature of double gate structure that have main gate and side gate. Could know current-voltage characteristic is superior in ultra low temperature (77 K) as well as in room temperature (300 K). Also, conditions of most suitable for get superior DG MOSFET's dynamic characteristics are main gate length of 50nm and side gate length of 70nm and could know that should be approved more than voltage 2V. Also, this DG MOSFET usefully use may as digital device because on-off characteristic is superior.

Characteristics analysis of Sub-50nm Double Gate MOSFET (Sub-50nm Double Gate MOSFET의 특성 분석)

  • 김근호;고석웅;이종인;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.486-489
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    • 2002
  • In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

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An Analysis for Gate-source Voltage of GaN HEMT Focused on Mutual Switch Effect in Half-Bridge Structure (GaN HEMT를 사용한 Half-Bridge 구조에서의 스위치 상호작용에 의한 게이트 전압분석)

  • Chae, Hun-Gyu;Kim, Dong-Hee;Kim, Min-Jung;Lee, Byoung Kuk
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.10
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    • pp.1664-1671
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    • 2016
  • This paper presents the analysis of the gate-source voltage of the gallium nitride high electronic mobility transistor (GaN HEMT) in the half bridge structure focused on the mutual effects of two switching operation. Especially low side gate-source voltage is analyzed mathematically according to the high side switch turn-on and turn-off operation. Moreover, the influence of each gate resistance and parasitic component on the switching characteristic of other side switch is investigated, and the formula, simulation and experimental results are compared with theoretical data.

Beyond-CMOS: Impact of Side-Recess Spacing on the Logic Performance of 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs

  • Kim, Dae-Hyun;del Alamo, Jesus A.;Lee, Jae-Hak;Seo, Kwang-Seok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.3
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    • pp.146-153
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    • 2006
  • We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

Pb, Cu, Zn Contaminants and Their Correlation of Soil, Leave and Bark of Ginkgo. B and Ambient Air Adjacent to a Heavy Traffic Road Side (교통량 과밀 도로주변의 토양과 가로수, 대기중 Pb, Cu, Zn 중금속 농도와 그 상관성에 관한 연구)

  • 박기학
    • Journal of Environmental Health Sciences
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    • v.18 no.2
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    • pp.19-25
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    • 1992
  • The study was carried out to investigate the correlation between the heavy metals emitted by the motor vehicles with the heavy traffic road side environment (soil, leave, bark, ambient air). The Pb, Cu, Zn contents in road side soil sand leaves, barks from Ginkgo, biloba and ambient air adjacent to the heavy traffic road side from June to August, 1992 Suwon city were analyzed by Atomic absorption spectrometry and Inductively coupled plasma emission spectrophotometry. The results were as follows: 1) The high levels of heavy metals concentration were Pb, at city-terminal in soil (186 $\mu$g/g), Cu, at city-terminal in soil (221 $\mu$g/g), Zn, at city-terminal in ambient air (252 $\mu$g/m$^{3}$). 2) The low leves of heavy metals concentration were Pb, at North-gate in ambient air (1.65$\mu$g/m$^{3}$), Cu, at North-gate in ambient air (4 $\mu$g/m$^{3}$), Zn, at North-gate in ambient air (15.31$\mu$g/m$^{3}$). 3) The regional distribution of Pb, Cu, Zn in road side soils, leaves and barks from Ginkgo, biloba, ambient air show high levels in turn, city4erminal, Guan Sean Dong, South gate, North gate. 4) The concentration of heavy metals (Pb, Cu, Zn) in soils, leaves, barks, ambient air was highly correlated with the traffic volume of the sampling sites (r=0.64~0.96). To conclude that the high levels of Pb, Cu, Zn contaminations were positively related to motor vehicles-borne pollutants and road side soils, trees, ambient air adjacent to a high density building area with low road coverage and heavy traffic volume were reflected strongly by the hazardous pollutants emitted by motor vehicles.

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40nm InGaAs HEMT's with 65% Strained Channel Fabricated with Damage-Free $SiO_2/SiN_x$ Side-wall Gate Process

  • Kim, Dae-Hyun;Kim, Suk-Jin;Kim, Young-Ho;Kim, Sung-Wong;Seo, Kwang-Seok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.1
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    • pp.27-32
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    • 2003
  • Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

A New EEPROM with Side Floating Gates Having Different Work Function from Control Gate

  • Youngjoon Ahn;Sangyeon Han;Kim, Hoon;Lee, Jongho;Hyungcheol Shin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.157-163
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    • 2002
  • A new flash EEPROM device with p^+ poly-Si control gate and n^+ poly-Si floating side gate was fabricated and characterized. The n^+ poly-Si gate is formed on both sides of the p^+ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

Second-Order G-equivariant Logic Gate for AND Gate and its Application to Secure AES Implementation (AND 게이트에 대한 2차 G-equivariant 로직 게이트 및 AES 구현에의 응용)

  • Baek, Yoo-Jin;Choi, Doo-Ho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.1
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    • pp.221-227
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    • 2014
  • When implementing cryptographic algorithms in mobile devices like smart cards, the security against side-channel attacks should be considered. Side-channel attacks try to find critical information from the side-channel infromation obtained from the underlying cryptographic devices' execution. Especially, the power analysis attack uses the power consumption profile of the devices as the side-channel information. This paper proposes a new gate-level countermeasure against the power analysis attack and the glitch attack and suggests how to apply the measure to securely implement AES.