JSTS:Journal of Semiconductor Technology and Science

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Beyond-CMOS: Impact of Side-Recess Spacing on the Logic Performance of 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs

  • Kim, Dae-Hyun (Microsystems Technology Laboratory (MTL), Massachusetts Institute of Technology (MIT)) ;
  • del Alamo, Jesus A. (Microsystems Technology Laboratory (MTL), Massachusetts Institute of Technology (MIT)) ;
  • Lee, Jae-Hak (Seoul National University) ;
  • Seo, Kwang-Seok (Seoul National University)
  • Published : 2006.09.30
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Abstract

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

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References

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