A New EEPROM with Side Floating Gates Having Different Work Function from Control Gate |
Youngjoon Ahn
(Department of Electrical Engineering and Computer Science, KAIST)
Sangyeon Han (Department of Electrical Engineering and Computer Science, KAIST) Kim, Hoon (Department of Electrical Engineering and Computer Science, KAIST) Lee, Jongho (School of Electrical Engineering, Wonkwang University) Hyungcheol Shin (Department of Electrical Engineering and Computer Science, KAIST) |
1 | S.Han, S.Chang, J.Lee, and S.Shin, '50nm MOSFET with electrically induced source/drain (S/D) extensions,' IEEE Trans. Electron Devices, vol.48, pp. 2058-2064, Sep. 2001 DOI ScienceOn |
2 | Silvaco International, ATLAS User's Manual Version 5.2.0.R, 2000 |
3 | V.N.Kynett et al, ' A 128 K flash EEPRM using double polysilicon technology,' Tech. Digest, 1987, ISSCC, pp. 76-77 |
4 | Y. Mizutani, K. Makita, 'Characteristics of a new EPROM cell structure with a sidewall floating gate,' IEEE Trans. Electron Devices, vol. ED-34, No. 6, pp. 1297-1303, Jun. 1987 |
5 | C. Papadas, B. Guillaumot, and B. Cialdella, 'A novel pseudo-floating-gate Flash EEPROM Device ( -Cell),' IEEE Electron Device Lett., vol.18, pp.319-322, Jul. 1997 DOI ScienceOn |
6 | P. Pavan, R. Bez, P.Olivo, E. Zazoni, 'Flash memory cells - an overview,' Proceedings of the IEEE, vol. 85, No. 8, Aug 1997, pp.1248-1271 DOI ScienceOn |