JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A New EEPROM with Side Floating Gates Having Different Work Function from Control Gate

  • Youngjoon Ahn (Department of Electrical Engineering and Computer Science, KAIST) ;
  • Sangyeon Han (Department of Electrical Engineering and Computer Science, KAIST) ;
  • Kim, Hoon (Department of Electrical Engineering and Computer Science, KAIST) ;
  • Lee, Jongho (School of Electrical Engineering, Wonkwang University) ;
  • Hyungcheol Shin (Department of Electrical Engineering and Computer Science, KAIST)
  • Published : 2002.09.01
Download PDF
⟨ Previous Next ⟩

Abstract

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.

Keywords

References

  1. P. Pavan, R. Bez, P.Olivo, E. Zazoni, 'Flash memory cells - an overview,' Proceedings of the IEEE, vol. 85, No. 8, Aug 1997, pp.1248-1271 https://doi.org/10.1109/5.622505
  2. V.N.Kynett et al, ' A 128 K flash EEPRM using double polysilicon technology,' Tech. Digest, 1987, ISSCC, pp. 76-77
  3. Y. Mizutani, K. Makita, 'Characteristics of a new EPROM cell structure with a sidewall floating gate,' IEEE Trans. Electron Devices, vol. ED-34, No. 6, pp. 1297-1303, Jun. 1987
  4. C. Papadas, B. Guillaumot, and B. Cialdella, 'A novel pseudo-floating-gate Flash EEPROM Device (${\Psi}$ -Cell),' IEEE Electron Device Lett., vol.18, pp.319-322, Jul. 1997 https://doi.org/10.1109/55.596924
  5. S.Han, S.Chang, J.Lee, and S.Shin, '50nm MOSFET with electrically induced source/drain (S/D) extensions,' IEEE Trans. Electron Devices, vol.48, pp. 2058-2064, Sep. 2001 https://doi.org/10.1109/16.944196
  6. Silvaco International, ATLAS User's Manual Version 5.2.0.R, 2000