• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1338-1342
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• 2011

In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of Digital Contents Society
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• v.7 no.2
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• pp.103-108
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• 2006

Short-range wireless communication and networking technologies are becoming increasingly important in enabling useful mobile applications. for example, ZigBee technology is expected to provide low cost and low power connectivity for equipment that needs battery life as long as several months to several years. In addition, ZigBee can be implemented in mesh networks larger than is possible with Bluetooth. The main features of this ZigBee standard are network flexibility, low cost, very low power consumption, and low data rate in an adhoc self-organizing network among fixed, portable and moving devices. Home network/Home automation is one of the key market areas for Zigbee, with an example of a simple network This paper investigates the effect of short range wireless channel on the performance of Zigbee system and DSSS-BPSK signal transmission in AWGN, interference and Rician fading environments. And we investigate performance degradation due to interference and fading effects in short range wireless channel. In particular, the impacts of the fading and interference level on the bit error probability is shown in BER performance figures.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.73-76
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• 2020

The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantum-mechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.20-27
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• 2010

Modeling is essential to simulate the operation of integrated circuit (IC) before its fabrication. Seeing a large number of Metal-Oxide-Silicon Field-Effect-Transistor (MOSFET) models available, it has become important to understand them and compare them for their pros and cons. The task becomes equally difficult when the complexity of these models becomes very high. The paper reviews the mainstream models with their physical relevance and their comparisons. Major short-channel and quantum effects in the models are outlined. Emphasis is set upon the latest compact models like BSIM, MOS Models 9/11, EKV, SP etc.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.