• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.389-391
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• 2011

This paper has been studied about design of linear 25Watt Power amplifier for VDR(VHF Data Radio). VDR's frequency band is 117.975~137MHz, and CSMA(Carrier Sense Multiple Access), D8PSK(Differential Eight Phase Shift Keyed), 25KHz's channel bandwidth use. It also stated in DO-281A MOPS output power, symbol constellation error, spurious emissions, adjacent channel power must be met. HPA is designed to meet DO-281A standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.1-8
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• 2000

In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.7
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• pp.675-683
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• 1991

When alpha particles are incident into the substrate, we have calculated the advanced current caused by collecting charges as a function of time, the energy of alpha particle, and the carrier concentration of the substrate. Employing SPICE, we have compared two circuits of which one has dummy cell and another has dummy line instead of dummy cell, and both are connected to the bit line node including sense amplifier and cell within the memory device. From the numerical analysis, (it may be conjectured that)the smaller energy of alpha particle and the lower concentration of the substrate, the more possibility of misoperation due to alpha particles. It may be also found that the effects of alpha particle are substantially reduced in the circuit without dummy cell.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.26-36
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• 2008

Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.1-7
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• 2010

In this paper, we suggested a sensing method of PoRAM with the multilevel cell When a specific voltage is applied between top and bottom electrodes of PoRAM unit cell, we can distinguish cell states by changing resistance values of the cell. Especially, we can use the PoRAM as the multilevel cell due to have four stable resistance values per cell. Therefore, we proposed an address decoding method, sense amplifier and control signal for sensing of a multilevel cell. The sense amplifier is designed based on a current comparator that compared a cell current the cell with a reference current, and have a low input impedance for a amplification of the current. The proposed circuit was designed in a $0.13{\mu}m$ CMOS technology, we verified to sense each data "00", "01", "10", "10" by four states of a cell current.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2451-2456
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• 2011

This paper is a study on the high power amplifier to fulfill standards of the MOPS. VDR's frequency band is 117.975~137MHz, and CSMA(Carrier Sense Multiple Access), D8PSK(Differential Eight Phase Shift Keyed), 25KHz's channel bandwidth use. It also stated in DO-281A MOPS output power, symbol constellation error, spurious emissions, adjacent channel power must be met. We designed and measured the performance. The 38dB of the IM3 satisfies the MOPS standard.

• Journal of IKEEE
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• v.25 no.2
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• pp.309-314
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• 2021

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.