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Comparative Analysis and Performance Evaluation of New Low-Power, Low-Noise, High-Speed CMOS LVDS I/O Circuits  

Byun, Young-Yong (Memory Div., Samsung Electronics)
Kim, Tae-Woong (Dept. of Electronics Engineering, Dongguk University)
Kim, Sam-Dong (Dept. of Electronics Engineering, Dongguk University)
Hwang, In-Seok (Dept. of Electronics Engineering, Dongguk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.45, no.2, 2008 , pp. 26-36 More about this Journal
Abstract
Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.
Keywords
LVDS; Sense amplifier; Differential amplifier; Impedance matching; Inductor;
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