DOI QR코드

DOI QR Code

Selective Operating Preamplifier Circuit for Low Voltage Static Random Access Memory

저전압 에스램용 선별 동작 사전 증폭 회로

  • Jeong, Hanwool (Dept. of Electronics Engineering, Kwangwoon University)
  • Received : 2021.05.18
  • Accepted : 2021.06.21
  • Published : 2021.06.30

Abstract

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

본 논문에서 제안된 에스램 사전 증폭 회로는 에스램 데이터 읽기 과정에서 감지 증폭을 활성화 하는 데 필요한 시간을 55% 감소함으로써 기존 회로 대비 읽기 속도를 현격히 개선하였다. 이는 사전 증폭 과정에서 공정 편차에 의한 트랜지스터의 성능 편차를 보상하는 고유 회로에 기인한 것이다. 뿐만 아니라, 사전 증폭으로 인한 추가 에너지 소모량을 최소화하기 위하여 사전 증폭이 필요한 경우에만 사전 증폭기를 활성화 할 수 있는 선별 활성화 회로를 제안하여 추가 에너지 소모를 4.45% 이내로 제한하였다.

Keywords

Acknowledgement

This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIT) (No. 2020R1G1A1009777)

References

  1. MJM. Pelgrom, et al., "Matching properties of MOS transistors," IEEE Journal of solid-state circuits, Vol.24, No.5: pp.1433-1439, 1989. DOI: 10.1109/JSSC.1989.572629
  2. B. Mohammad, et al. "Comparative study of current mode and voltage mode sense amplifier used for 28nm SRAM.," 2012 24th International Conference on Microelectronics (ICM). IEEE, pp.1-6, 2012. DOI: 10.1109/ICM.2012.6471396
  3. H. Jeong et al. "Bitline precharging and preamplifying switching pMOS for high-speed low-power SRAM," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.63, No.11, pp.1059-1063, 2016. DOI: 10.1109/TCSII.2016.2548100
  4. L. T. Clark, et al., "ASAP7: A 7-nm FinFET Predictive Process Design Kit," Microelectronics Journal, vol.53, pp.105-115, 2016. DOI: 10.1016/j.mejo.2016.04.006
  5. T. S. Doorn, et al. "Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield," ESSCIRC 2008-34th European Solid-State Circuits Conference. IEEE, pp.230-233, 2008. DOI: 10.1109/ESSCIRC.2008.4681834