• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.47-54
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• 2005

In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, ${\Delta}Cc$ by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that ${\Delta}Cc$ is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk ${\Delta}Cc$ is always larger than Cc while for in-phase crosstalk ${\Delta}Cc$ is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.88-93
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• 2004

We, for the first time, present novel test patterns and conclusive on-chip data indicating that the variation of coupling capacitance, ${\Delta}C_C$ by crosstalk can be larger than static coupling capacitance, $C_C$. The test chip is fabricated using a generic 150 nm CMOS technology with 7 level metallization. It is also shown that ${\Delta}C_C$ is strongly dependent on the phase of aggressive lines. For antiphase crosstalk ${\Delta}C_C$ is always larger than $C_C$ while for in-phase crosstalk $D_{\Delta}C_C$is smaller than $C_C$.

• Journal of Industrial Technology
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• v.22 no.A
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• pp.89-94
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• 2002

In this paper, a Exhaust Flow Controller (EFC) technology for uniform application of film coater and developer device is introduced that spread and remove photo resister at semiconductor manufacturing process. Because developed EFC device uses differential pressure sensing method as a differential flow meter and embodied smart A/D conversion by using a one chip microprocessor and devised by feedback Servo control, It has shown excellent performance and stability evaluation, as maximum 2000L/min flow, capability of installation to actual semiconductor equipment.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.5-11
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• 2006

One of the most important is to insure that a new circuit design is qualified far release before it is scheduled for manufacturing, test, assembly and delivery. Due to various causes, there happens to be a low yield in the wafer process. Wafer test is a critical process in analyzing the chip characteristics in the EDS(electric die sorting) using analytic tools -wafer map, wafer summary and datalog. In this paper, we propose new analytic map algorithms for DDI chip test data. Using the proposed analytic map algorithms, we expect to improve the yield, quality and analysis time.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.38-44
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• 1999

In this paper, we have constructed a self-diagnostic circuit which could detect erroneous signals in most cases that a eight-beam piezoresistive accelerometer were destroyed more than its one beam. To confirm the function of the circuit, PSPICE simulation was carried out. An IC chip was fabricated with a layout of KA 324 amplifier using a bipolar standard processing. After a package of the chip was sealed using a plastic package with 24 pins, the self-diagnostic characteristics were investigated. Then, the measured self-diagnostic characteristics of the circuit were compared with the PSPICE simulated result.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.65-70
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• 2013

A 0.18-${\mu}m$ 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving electrical overstress (EOS) robustness. The improved cell array consists of 20 GGNMOS, 4 inserted well taps, 2 end-well taps and shallow trench isolation (STI). Technology computer-aided design (TCAD) simulation results show that the inserted well taps and extended drain contact gate spacing (DCGS) is effective in preventing EOS failure, e.g. local burnout. Thermodynamic models for device simulation enable us to obtain lattice temperature distributions inside the cells. The peak value of the maximum lattice temperature in the improved GGNMOS cell array is lower than that in a conventional GGNMOS cell array. The inserted well taps also improve the uniformity of turn-on of GGNMOS cells. EOS test results show the validity of the simulation results on improvement of EOS robustness of the new GGNMOS I/O cell array.