Browse > Article

Analysis of Crosstalk-Induced Variation of Coupling Capacitance between Interconnect lines in High Speed Semiconductor Devices  

Ji Hee-Hwan (Dept. of Electronics Engineering, Chungnam National Univ.)
Han In-Sik (Dept. of Electronics Engineering, Chungnam National Univ.)
Park Sung-Hyung (MagnaChip Semiconductor, Inc.)
Kim Yong-Goo (MagnaChip Semiconductor, Inc.)
Lee Hi-Deok (Dept. of Electronics Engineering, Chungnam National Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.5, 2005 , pp. 47-54 More about this Journal
Abstract
In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, ${\Delta}Cc$ by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that ${\Delta}Cc$ is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk ${\Delta}Cc$ is always larger than Cc while for in-phase crosstalk ${\Delta}Cc$ is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.
Keywords
Crosstalk; Interconnect; Coupling capacitance; Nano-CMOS;
Citations & Related Records
연도 인용수 순위
  • Reference
1 H. D. Lee, M.J. Iang, D. G. Kang, J. M. Hwang, Y. J. Kim, O. K. Kwon, and D. M. Kim, 'Characterization of Crosstalk-Induced Noise for 0.18um CMOS Technology with 6-Level Metallization Using Time Domain Reflectometry and S-Parameters', in IEDM Tech. Dig., 1999, pp. 905-908   DOI
2 F. Moll, M. Roca and A. Rubio, 'Measurement of crosstalk-induced delay errors in integrated circuits', Electronics Letters, vol. 33, no. 19, pp. 1623-1624, Sept. 1997   DOI
3 T. Sakurai, 'Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSIs', IEEE Trans. Electron Devices, vol. 40, No.1, pp. 118-124, Jan. 1993   DOI   ScienceOn
4 K. Yamashita, S. Odanaka, 'Impact of Crosstalk on Delay Time and a Hierarchy of Interconnects', in IEDM Tech. Dig., 1998, pp. 291-294   DOI
5 J. A. Davis, V. V. De, and J. D. Meindl, 'A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) Part I: Derivation and Validation', IEEE Trans. Electron Devices, vol. 45, pp. 580-589, Mar. 1998   DOI   ScienceOn
6 S. K. H. Fung, et. al, '65nm CMOS High Speed, General Purose and Low Power Transistor Technology for High Volume Foundry Application', in Tech. Symposium of VLSI Technology, 2004, pp. 92-93   DOI
7 M. T. Bohr, 'Interconnect Scaling The Real Limiter to High Performance ULSI', in IEDM Tech. Dig., 1995, pp. 241-244   DOI
8 S. Y. Oh and K. J. Chang, '2001 Needs for Multi-Level Interconnect Technology', IEEE Cirsuits & Devices, pp. 16-21, Jan. 1995   DOI
9 D. H. Cho, Y. S. Eo, M. H. Seung, N. H. Kim, J. K. Wee, O. K. Kwon, and H. S. Park, 'Interconnect Capacitance, Crosstalk, and Signal Delay for 0.35 mm CMOS Technology', in IEDM Tech. Dig., 1996, pp. 619-622   DOI
10 H. D. Lee, M. J. Jang, and D. M. Kim 'On-Chip Characterization of Interconnect Parameters and Time Delay in 0.18 um CMOS Technology for ULSI Circuit Applications', IEEE Trans. Electron Devices, vol. 46, No.5, pp. 1073-1079, May 2000   DOI   ScienceOn
11 K. Yamashita, S. Odanaka, K. Egashira, and T. Ueda, 'On-Chip Interconnect Evaluation on Delay Time Increase by Crosstalk', in IEDM Tech. Dig., 1999, pp. 631-634   DOI
12 H. D. Lee, M. J. Jang, D. G. Rang, J. M. Hwang, Y. J. Kim, O. K. Kwon, and D. M. Kim, 'Characterization of Crosstalk-Induced Noise for 0.18 um CMOS Technology with 6-Level Metallization Using Time Domain Reflectometry and S-Parameters', in IEDM Tech. Dig., 1999, pp. 905-908   DOI
13 H. B. Bakoglu, Circuits, Interconnection, and Packaging for VLSI, Addison-Wesley Publishing Co., 1990
14 K. Yamashita, S. Odanaka, K. Egashira, and T. Ueda, 'On-Chip Interconnect Evaluation on Delay Time Increase by Crosstalk', in IEDM Tech. Dig., 1999, pp. 631-634   DOI
15 A. B. Kahng, S. Muddu, and E. Sarto, 'On Switch Factor Based Analysis of Coupled RC Interconnects', in Proc. Design Automation Conference, 2000, pp. 79-84   DOI
16 H. D. Lee, M. J. Jang, D. G. Rang, Y. J. Lee, J. M. Hwang, and D. M. Kim, 'Real Time On-Chip Characterization of Time Delay Arising from Multi-Level-Metallization : Decoupling of Pure Charging and Drift-and-Charging', in IEDM Tech. Dig., 1998, pp. 287-290   DOI