• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.241-245
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• 2022

In this study, we measured and comparatively analyzed the characteristics of MPS (Merged Pin Schottky) diodes in 4H-SiC by changing the areal ratio between the Schottky and PN junction region. Increasing the temperature from 298 K to 473 K resulted in the threshold voltage shifting from 0.8 V to 0.5 V. A wider Schottky region indicates a lower on-resistance and a faster turn-on. The effective barrier height was smaller for a wider Schottky region. Additionally, the depletion layer became smaller under the influence of the reduced effective barrier height. The wider Schottky region resulted in the ideality factor being reduced from 1.37 to 1.01, which is closer to an ideal device. The leakage saturation current increased with the widening Schottky region, resulting in a 1.38 times to 2.09 times larger leakage current.

• 대한전자공학회논문지SD
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• 제39권10호
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• pp.25-34
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• 2002

본 논문에서는 코발트 실리사이드가 형성된 얕은 p+-n과 n+-p 접합의 전류-전압 특성을 분석하여 silicidation에 의해 형성된 Schottky contact 면적을 구하였다. 역방향 바이어스 영역에서는 Poole-Frenkel barrier lowering 효과가 지배적으로 나타나서 Schottky contact 효과를 파악하기가 어려웠다. 그러나 Schottky contact의 형성은 순방향 바이어스 영역에서 n+-p 접합의 전류-전압 (I-V) 동작에 영향을 미치는 것으로 확인되었다. 실리사이드가 형성된 n+-p 다이오드의 누설전류 증가는 실리사이드가 형성될 때 p-substrate또는 depletion area로 코발트가 침투퇴어 Schottky contact을 형성하거나 trap들을 발생시켰기 때문이다. 분석결과 perimeter intensive diode인 경우에는 silicide가 junction area까지 침투하였으며, area intensive junction인 경우에는 silicide가 비록 공핍층이나 p-substrate까지 침투하지는 않았더라도 공핍층 근처까지 침투하여 trap들을 발생시켜 누설전류를 증가시킴을 확인하였다. 반면 p+-n 다이오드의 경우 Schottky contact이발생하지 않았고 따라서 누설전류도 증가하지 않았다. n+-p 다이오드에서 실리사이드에 의해 형성된 Schottky contact 면적은 순방향 바이어스와 역방향 바이어스의 전류 전압특성을 동시에 제시하여 유도할 수 있었고 전체 접합면적의 0.01%보다 작게 분석되었다.

• 대한전자공학회논문지
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• 제23권4호
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• pp.484-489
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• 1986

A device with variable stepped oxide layer along the edge region of Schottky junction have been designed and fabricated. The effect of this stepped oxide layer in the edge region improves the breakdown voltage as a result of the by increase of the depletion layer width, and decreases the leakage current as compared to the effect of conventional field oxide layer, when the reverse voltage was applied. Experimental results shown that the Schottky diode with the the reverse voltage was applied. Experimenal results show that the Schottky diode with the optimal stepped oxide layer maintains nearly ideal I-V characteristics and excellent breakdown voltage(170V) by reducing the edge effect inherent in metal-semiconductor contacts. The optimal conditions of stepped oxide layer are 1700\ulcornerin thickness and 10\ulcorner in length.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.343-343
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• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• 반도체디스플레이기술학회지
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• 제17권2호
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• pp.32-35
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• 2018

The current voltage characteristics of ZTO/SiOC were researched, and the conductivities of the ZTO films as a channel material were analyzed. The current of SiOC was abruptly decreased near 0V, and then the depletion layer was formed by the disappearance of charges in the region form -12V to +12V. SiOC with Schottky contacts near ${\sim}10^{-9}$ A had the cutoff effect of leakage currents. The conductivity of ZTOs prepared on SiOC was improved in the cutoff region of the leakage current of -12V

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.664-674
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• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• 센서학회지
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• 제26권2호
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• 대한전자공학회논문지
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• 제25권7호
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• pp.774-779
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• 1988

The homo and hetero-junction diodes were fabricated using BP-Si structure. After removal of Si substrates, schottky diodes were fabricated on the BP bulk. The electrical properties of the diode were examined through current-voltage characteristics curve. The schottky diode with Sb electrode has a cut-in voltage of 0.33V. This value is almost equal to that of the typical schottky diodes. The breakdown voltage of the schottky diode is 30V. When BP was used for photo cell as a window, the conversion efficiency improved from 6.5% to 8.3%, and optical transmissivity of BP invreased in short wavelength region.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.938-940
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• 1999

We have fabricated SiC Schottky diode for high temperature applications. SiC thin film for drift region has been deposited by ICP-CVD. In order to establish metallization conditions, we have extracted the device parameters of the Schottky diode from the forward I-V characteristics and the C-V characteristics as a function of temperature. The ideality factor was varied from 2.07 to 1.15 and the barrier height was also varied from 1.26eV to 1.92eV with increase of temperature. The reverse blocking voltage was 183 V.