• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Investigative Magnetic Resonance Imaging
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• v.19 no.4
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• pp.212-217
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• 2015

Purpose: For a single time-point hyperpolarized $^{13}C$ magnetic resonance spectroscopy imaging (MRSI) of animal models, scan-time window after injecting substrates is critical in terms of signal-to-noise ratio (SNR) of downstream metabolites. Pre-scans of time-resolved magnetic resonance spectroscopy (MRS) can be performed to determine the scan-time window. In this study, based on two-site exchange model, protocol-specific simulation approaches were developed for $^{13}C$ MRSI and the optimal scan-time window was determined to maximize the SNR of downstream metabolites. Materials and Methods: The arterial input function and conversion rate constant from injected substrates (pyruvate) to downstream metabolite (lactate) were precalibrated, based on pre-scans of time-resolved MRS. MRSI was simulated using two-site exchange model with considerations of scan parameters of MRSI. Optimal scan-time window for mapping lactate was chosen from simulated lactate intensity maps. The performance was validated by multiple in vivo experiments of BALB/C nude mice with MDA-MB-231 breast tumor cells. As a comparison, MRSI were performed with other scan-time windows simply chosen from the lactate signal intensities of pre-scan time-resolved MRS. Results: The optimal scan timing for our animal models was determined by simulation, and was found to be 15 s after injection of the pyruvate. Compared to the simple approach, we observed that the lactate peak signal to noise ratio (PSNR) was increased by 230%. Conclusion: Optimal scan timing to measure downstream metabolites using hyperpolarized $^{13}C$ MRSI can be determined by the proposed protocol-specific simulation approaches.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.12
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• pp.675-682
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• 2000

When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Korean Journal of Clinical Laboratory Science
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• v.36 no.2
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• pp.193-198
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• 2004

PET/CT combines the functional information from a positron emission tomography (PET) exam with the anatomical information from a computed tomography (CT) exam into one single exam. A CT scan uses a combination of x-rays and computers to give the radiologist a non-invasive way to see inside your body. One advantage of CT is its ability to rapidly acquire two-dimensional pictures of your anatomy. Using a computer these 2-D images can be presented in 3-D for in-depth clinical evaluation. A PET scan detects changes in the cellular function - how your cells are utilizing nutrients like sugar and oxygen. Since these functional changes take place before physical changes occur, PET can provide information that enables your physician to make an early diagnosis. The PET exam pinpoints metabolic activity in cells and the CT exam provides an anatomical reference. When these two scans are fused together, your physician can view metabolic changes in the proper anatomical context of your body. PET/CT offers significant advantages including more accurate localization of functional abnormalities, and the distinction of pathological from normal physiological uptake, and improvements in monitoring treatment. A PET/CT scan allows physicians to measure the body's abnormal molecular cell activity to detect cancer (such as breast cancer, lung cancer, colorectal cancer, lymphoma, melanoma and other skin cancers), brain disorders (such as Alzheimer's disease, Parkinson's disease, and epilepsy), and heart disease (such as coronary artery disease).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1151-1156
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• 2009

Unstable sustain discharges can occur at the bottom cells of the panel at high temperature. To solve this problem, the wall charge variation during an address period was investigated. A test panel of 7.5 inch XGA level was used and one green cell was measured. In order to realize operating condition equal to that of the bottom cells of 50 inch panel, the addressing stress pulses are applied. It seems that the resultant wall charge loss during address period increased with increase of stress time, temperature, pressure and Xe %. Wall charge loss increases with potential difference between scan electrode and address electrode, therefore wall charge loss can be minimized by the increase of scan voltage during address period.

• Journal of Information Display
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• v.2 no.2
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• pp.39-44
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• 2001

The conditions of the wall charges and priming particles in a unit discharge cell in AC PDP seriously affect the addressing discharge characteristics in the driving method with ramped setup pulse. Moreover, the discharge conditions at the end of the scan line may be different from the first scan line because of the difference of about 1ms address time. Consequently, the addressing time and its dispersion may be different for any two discharge cells that lead to misfiring and the increase in the total addressing time. In order to improve the addressing time and its dispersion, we have applied different addressing voltage at each cell such as progressively increase pulse voltage instead of constant one. As a result, the addressing time and its dispersion of all cells were improved by about 30% compared with the conventional driving method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.