• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.487-490
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• 2007

In this paper, the formation and thermal stability characteristics of Ni silicide using Ni-V alloy on Boron cluster ($B_{18}H_{22}$) implanted bulk and SOI substrate were examined in comparison with pure Ni for nano-scale CMOSFET. The Ni silicide using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate after high temperature post-silicidation annealing showed the lower sheet resistance, no agglomeration interface image and lower surface roughness than that using pure Ni. The thermal stability of Ni silicide was improved by using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.3
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• pp.228-233
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• 2001

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro elelctro mechanical system) applications usign SOI (Si-on-insulator) and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10㎛ thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro-heater was fabricated with Pt-RTD (resistance thermometer device) on the same substrate by suing MgO as medium layer. The thermal characteristics of the micro-heater wit the SOI membrane is 280$\^{C}$ at input power 0.9W; for the SOI membrane with 10 trenches, it is 580$\^{C}$ due to reduction of the external thermal loss. Therefore, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.178-180
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• 1993

The back bias effect on the breakdown voltage of SOI $p^+$-n diode is investigated. The breakdown voltage of the SOI $p^+$-n diode increases with the applied back bias. When the cathode electrode is used as a back bias, it is necessary to put the dielectric material between the Si-substrate and the bottom cathode electrode.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.294-300
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• 2002

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using $1.5{\mu}m$ CMOS process. The voltage gain of fabricated amplifier was about two hundred.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1039-1044
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• 2002

Film Bulk Acoustic Resonator (FBAR) using thin piezoelectric films can be made as monolithic integrated devices with compatibility to semiconductor process, leading to small size, low cost and high Q RF circuit elements with wide applications in communications area. This paper presents an MMIC compatible suspended FBAR using SOI micromachining. It is possible to make a single crystal silicon membrane using a SOI wafer In fabricating active devices, SOI wafer offers advantage which removes the substrate loss. FBAR was made on the 12㎛ silicon membrane. Electrode and Piezoelectric materials were deposited by RF magnetron sputter. The maximum resonance frequency of FBAR was shown at 2.5GHz range. The reflection loss, K$^2$$\_$eff/, Q$\_$serise/ and Q$\_$parallel/ in that frequency were 1.5dB, 2.29%, 220 and 160, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.11-12
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• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.331-340
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• 1994

Polysilicon on insulator has been recrystallized by zone melting recrystallization method with graphite strip heaters. Experiments are performed with non-seed SOI structures. When the capping layer thickness of Si$\_$3/N$\_$4//SiO$\_$2/ is 2.0.mu.m, grain boundaries are about 120.mu.m spacing and protrusions reduced. After the seed SOI films are annealed at 1100.deg. C in NH$\_$3/ ambient for 3 hours, the recrystallized silicon surface has convex shape. After ZMR process, the tensile stress is 2.49*10$\^$9/dyn/cm$\^$2/ and 3.74*10$\^$9/dyn/cm$\^$2/ in the seed edge and seed center regions. The phenomenon of convex shape and tensile stress difference are completely eliminated by using the PSG/SiO$\_$2/ capping layer. The characterization of SOI films are showed that the SOI films are improved in wetting properties. N channel SOI MOSFET has been fabricated to investigate the electrical characteristics of the recrystallized SOI films. In the 0.7.mu.m thickness SOI MOSFET, kink effects due to the floating substrate occur and the electron mobility was calculated from the measured g$\_$m/ characteristics, which is about 589cm$\^$2//V.s. The recrystallized SOI films are shown to be a good single crystal silicon.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.189-194
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• 2018

Nowadays most integrated circuits are built using the bulk CMOS technology, but it has much difficulty in further reduction of the power consumption and die size. As a super low-power technology to solve such problems, the SOI technology attracts great attention recently. In this paper, the study results of the temperature dependency of the hot carrier effects in the n-channel MOSFETs fabricated on the thin SOI substrate were discussed. In spite that the devices employed the LDD structure, the hot carrier effects were more serious than expected due to the high series resistance between the channel region and the substrate contact to the ground, and were found to be less serious for the higher temperature with the more phonon scattering in the channel region, which resulted in reducing the hot electron generation.