• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.383-386
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• 1988

In MOS integrated circuits, annealing after oxidation process is necessary to improve physical properties of silicon dioxide. With subsequent annealing in inert gases such as nitrogen or argon, and excess silicon bond is allowed time to complete the oxidation and surface charge density is reduced. In this paper, we will present effects of the rapid thermal annealing on silicon dioxide. In order to evaluate characteristics of silicon dioxide, we analyzed C-V curve dependent on annealing time and temperature, and presented variation of fixed oxide charge.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.79-83
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• 2009

In this study, the characteristics of amorphous silicon etching for the formation of gate electrodes have been evaluated at the variation of several process parameters. When total flow rates composed of $Cl_2/HBr/O_2$ gas mixtures increased, the etch rate of amorphous silicon layer increased, but critical dimension (CD) bias was not notably changed regardless of total flow rate. As the amount of HBr in the mixture gas became larger, amorphous silicon etch rate was reduced by the low reactivity of Br species. In the case of increasing oxygen flow rate, etch selectivity was increased due to the reduction of oxide etch rate, enhancing the stability of silicon gate etching process. However, gate electrodes became more sloped according to the increase of oxygen flow rate. Higher source power induced the increase of amorphous silicon etch rate and CD bias, and higher bias power had a tendency to increase the etch rate of amorphous silicon and oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Bulletin of the Korean Chemical Society
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• v.33 no.1
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• pp.83-89
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• 2012

Due to the potential importance and usefulness, usage of highly ordered nanoporous anodized aluminum oxide can be broadened in industry, when highly ordered anodized aluminum oxide can be placed on a substrate with controlled thickness. Here we report a facile route to highly ordered nanoporous alumina with the thickness of hundreds-of-nanometer on a silicon wafer substrate. Hexagonally or tetragonally ordered nanoporous alumina could be prepared by way of thermal imprinting, dry etching, and anodization. Adoption of reusable polymer soft molds enabled the control of the thickness of the highly ordered porous alumina. It also increased reproducibility of imprinting process and reduced the expense for mold production and pattern generation. As nanoporous alumina templates are mechanically and thermally stable, we expect that the simple and costeffective fabrication through our method would be highly applicable in electronics industry.

• The Korean Journal of Ceramics
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• v.4 no.4
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• pp.304-310
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• 1998

Carbothermal reduction has been one of the important processes for the production of ceramic raw materials such as silicon carbide, silicon nitride, boron carbide, etc. The process has also been one of several trials for the recovery of ZnO from ZnO-containing waste. It usually involves two consecutive steps: the evolution of Zn vapor and its oxidation with air. In this study a ZnO-containing raw material is reduced by carbon at $1250^{\circ}C$ and the evolved Zn vapor is oxidized with air, resulting in fine powders of ZnO. computer programs, THERMO and PYROSIM developed by MINTEK, are used to simulate the process thermodynamically and the results are compared with the experimental results. It is shown that the ZnO-containing raw material can be reduced and can form fine ZnO with the yield as high as 98.7% under a proper condition. Based on these results, a process is engineered for the production of ZnO in a rotary kiln at a rate of 3 tons/day. The produced ZnO powders show properties suitable to the usual applications in ceramic industries with a purity of > 95wt% and an average particle size of ∼3${\mu}m$.

• Journal of the Korean Ceramic Society
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• v.38 no.12
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• pp.1132-1136
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• 2001

A silicon-substituted hydroxyapatite was prepared using tetraethylorthosilicate as a silicon source to obtain a biomaterial having an improved biocompatibility. From the XRD analysis, it was confirmed that a single-phase hydroxyapatite containing silicon was formed without revealing the presence of extra phases related to silicon oxide or other calcium phosphate species. Silicon content was up to 3.32% by weight. Through $\^$29/Si MAS NMR investigation we could confirm the presence of tetrahedral silicate in the framework of hydroxyapatite structure. Substitution of silicon into the hydroxyapatite framework (Ca$\_$10/(PO$_4$)$\_$6-x/(SiO$_4$)$\_$x/(OH)$\_$2-x/ reduced the amount of hydroxyl group to compensate for the extra negative charge of the silicate group, which is confirmed by FT-IR.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.430-430
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• 2012

The surface recombination velocity of the silicon solar cell could be reduced by passivation with insulating layers such as $SiO_2$, SiNx, $Al_2O_3$, a-Si. Especially, the aluminium oxide has advantages over other materials at rear surface, because negative fixed charge via Al vacancy has an additional back surface field effect (BSF). It can increase the lifetime of the hole carrier in p-type silicon. The aluminium oxide thin film layer is usually deposited by atomic layer deposition (ALD) technique, which is expensive and has low deposition rate. In this study, ICP-assisted reactive magnetron sputtering technique was adopted to overcome drawbacks of ALD technique. In addition, it has been known that by annealing aluminium oxide layer in nitrogen atmosphere, the negative fixed charge effect could be further improved. By using ICP-assisted reactive magnetron sputtering technique, oxygen to nitrogen ratio could be precisely controlled. Fabricated aluminium oxy-nitride (AlON) layer on silicon wafers were analyzed by x-ray photoelectron spectroscopy (XPS) to investigate the atomic concentration ratio and chemical states. The electrical properties of Al/($Al_2O_3$ or $SiO_2/Al_2O_3$)/Si (MIS) devices were characterized by the C-V measurement technique using HP 4284A. The detailed characteristics of the AlON passivation layer will be shown and discussed.