• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.509-514
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• 2004

This paper introduces the modified slip energy recovery system in order to improve its power factor and to reduce harmonics of line current waveforms. Twelve pulse line commutated converter with the chopper type IGBT is applied where the chopper is applied across the DC terminal and the chopped DC is fed to the converter operating as an inverter and then passed through the wye-wye and delta-wye transformer circuit. This scheme leads to be able to adjust the speed of the motor by the duty cycle of the chopper operating in PWM mode. The fuzzy logic controller is also introduced to the modified slip energy recovery system for keeping the motor speed to be constant when the load varies. The experimental results in testing the 0.22 kW wound rotor induction motor from no-load condition to rated condition show the effectiveness of the proposed control scheme.

• 한국안전학회지
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• 제36권4호
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• pp.1-11
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• 2021

Piping systems comprising pumps and valves are essential in the power plant, oil, and defense industry. Their purpose includes a stable supply of the working fluid or ensuring the target system's safe operation. However, piping system accidents due to leakage of toxic substances, explosions, and natural disasters are prevalent In addition, with the limited maintenance personnel, it becomes difficult to detect, isolate, and reconfigure the damage of the piping system and recover the unaffected area. An autonomous recovery piping system can play a vital role under such circumstances. The autonomous recovery algorithms for the piping system can be divided into low-pressure control algorithms, hydraulic resistance control algorithms, and flow inventory control algorithms. All three methods include autonomous opening/closing logic to isolate damaged areas and recovery the unaffected area of piping systems. However, because each algorithm has its strength and weakness, appropriate application considering the overall design, vital components, and operating conditions is crucial. In this regard, preliminary research on algorithm's working principle, its design procedures, and expected damage scenarios should be accomplished. This study examines the characteristics of algorithms, the design procedure, and working logic. Advantages and disadvantages are also analyzed through simulation results for a simplified piping system.

• 제어로봇시스템학회논문지
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• 제8권8호
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• pp.706-712
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• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.85-88
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• 2000

In order to resolve problems according to the phase error in QPSK demodulator of the digital communication systems. The demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the complexity of implementation is reduced by the reduction into half of the number of the multiplier in filter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table , We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is 175㎼, NCO with the proposed structure is 24.65㎼. As the result, it is recognized that about one eight of loss power is reduced. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.165-168
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• 2001

In this W the complexity of implementation is reduced by the reduction into half of the number of the multiplier in filter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table, We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is 175${\mu}$W, NCO with the proposed of structure is 24,65${\mu}$W. As if result, it is recognized that about one eight of loss power is reduced In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• 대한임베디드공학회논문지
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• 제12권4호
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• 한국자동차공학회논문집
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• 제10권2호
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• pp.101-116
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• 2002

Modern vehicles require a high degree of refinement, including good driveability to meet customer demands. Vehicle driveability, which becomes a key decisive factor for marketability, is affected by many parameters such as engine control and the dynamic characteristics in drive lines. Therefore, Engine and drive train characteristics should be considered to achieve a well balanced vehicle response simultaneously. This paper describes analysis procedures using a mathematical model which has been developed to simulate spark timing control logic. Inertia mass moment, stiffness and damping coefficient of engine and drive train were simulated to analyze the effect of parameters which were related vehicle dynamic behavior. Inertia mass moment of engine and stiffness of drive line were shown key factors for the shuffle characteristics. It was found that torque increase rate, torque reduction rate and torque recovery timing and rate influenced the shuffle characteristics at the tip-in condition for the given system in this study.

• 한국통신학회논문지
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• 제35권12C호
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• pp.1029-1034
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• 2010

QPSK 디지털 수신기는 전송 경로 또는 송수신기 간의 클럭 차이에 의해 발생하는 위상 편차를 보정하기 위해 위상 복원 방안이 필요하다. 널리 사용되고 있는 디지털 Costas 위상 복원 루프는 입력신호의 주파수/위상 복원 성능이 입력 신호의 전력에 따라 달라지므로 별도의 자동 이득조정 (AGC) 루프가 필요하고, 이는 하드웨어 구현시 시스템의 복잡도와 사용 자원을 증가시킨다. 본 논문에서는 입력 전력에 관계없이 일정한 위상 보정 기능을 수행할 수 있으며 타이밍 복원을 위한 AGC를 동시에 제공할 수 있는 위상 보정 및 진폭 보상 방안을 제안하였다. 제안된 방안은 CORDIC 알고리즘을 사용하여 입력 신호의 위상 및 진폭 정보를 분리하여 각각 처리하며 시스템의 복장도 및 사용 자원을 대폭 절감할 수 있으며, C++ 및 Model Sim을 사용한 모의실험을 통해 본 논문에서 제안한 위상 복원 루프의 동작을 검증하였다.