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http://dx.doi.org/10.5302/J.ICROS.2002.8.8.706

Synthesis of Deadlock-Free Ladder Diagrams for PLCs Based on Deadlock Detection and.Recovery (DDR) Algorithm  

Cha, Jong-Ho (Dept.of Electric Electronics Information System Engineering, University of Ulsan)
Cho, Kwang-Hyun (Dept.of Electric Electronics Information System Engineering, University of Ulsan)
Publication Information
Journal of Institute of Control, Robotics and Systems / v.8, no.8, 2002 , pp. 706-712 More about this Journal
Abstract
In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.
Keywords
FMS; PLC; Petri net; LD; MAPN; MTPL; ECC; deadlock; DDR algorithm;
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