Browse > Article
http://dx.doi.org/10.5573/JSTS.2012.12.3.341

Energy Efficient Processing Engine in LDPC Application with High-Speed Charge Recovery Logic  

Zhang, Yimeng (Graduate School of Information, Production and Systems, Waseda University)
Huang, Mengshu (Graduate School of Information, Production and Systems, Waseda University)
Wang, Nan (Graduate School of Information, Production and Systems, Waseda University)
Goto, Satoshi (Graduate School of Information, Production and Systems, Waseda University)
Yoshihara, Tsutomu (Graduate School of Information, Production and Systems, Waseda University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.12, no.3, 2012 , pp. 341-352 More about this Journal
Abstract
This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.
Keywords
Adiabatic logic; boost logic; low energy dissipation; processing engine;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Y. Zhang, L. Okamura, and T. Yoshihara, "An energy efficiency 4-bit multiplier with two-phase non-overlap clock driven charge recovery logic," Electronics, IEICE Transactions on, vol. E94-C, no. 4, pp. 605-612, April 2011.   DOI
2 L. Chen, J. Xu, I. Djurdjevic, and S. Lin, "Nearshannon-limit quasicyclic low-density parity-check codes," Communications, IEEE Transactions on, vol. 52, no. 7, pp. 1038-1042, july 2004.   DOI   ScienceOn
3 A. Darabiha, A. Chan Carusone, and F. Kschischang, "Power reduction techniques for LDPC decoders," Solid-State Circuits, IEEE Journal of, vol. 43, no. 8, pp. 1835-1845, aug. 2008.   DOI   ScienceOn
4 Y. Zhang, M. Huang, N. Wang, S. Goto, and T. Yoshihara, "A 1pJ/cycle processing engine in LDPC application with charge recovery logic," Solid-State Circuits Conference, 2011. A-SSCC 2011. IEEE Asian, pp. 213-216, Nov 2011.
5 J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons, INC., 2002.
6 Y. Moon and D. K. Jeong, "Efficient charge recovery logic," VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on, pp. 129-130, Jun. 1995.
7 D. Suvakovic and C. Salama, "Two phase nonoverlapping clock adiabatic differential cascode voltage switch logic (adcvsl)," Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International, pp.364-365, 2000.
8 H. Jianping, C. Lizhang, and L. Xiao, "A new type of low-power adiabatic circuit with complementary pass-transistor logic," ASIC, 2003. Proceedings. 5th International Conference on, vol. 2, pp. 1235-1238 Vol. 2, Oct. 2003.
9 Y. Ye and K. Roy, "Qserl: quasi-static energy recovery logic," Solid-State Circuits, IEEE Journal of, vol. 36, no. 2, pp. 239-248, Feb. 2001.   DOI   ScienceOn
10 V. De and J. Meindl, "Complementary adiabatic and fully adiabatic mos logic families for gigascale integration," Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International, pp. 298-299, 461, Feb. 1996.
11 Y. Takahashi, K. Konta, K. Takahashi, M. Yokoyama, K. Shouno, and M. Mizunuma, "Carry propagation free adder/subtracter using adiabatic dynamic cmos logic circuit technology," Fundamentals of Electronics, Communications and Computer Sciences, IEICE Transactions on, vol.E86-A, no.6, pp. 1437-1444, Jun 2003.
12 Y. Takahashi, T. Sekine, and M. Yokoyama, "VLSI implementation of a 4x4-bit multiplier in a two phase drive adiabatic dynamic CMOS logic," Electronics, IEICE Transactions on, vol. E90-C, no. 10, pp. 2002-2006, Oct 2007.   DOI
13 J. C. Kao, W. H. Ma, V. S. Sathe, and M. Papaefthymiou, "Energyefficient low-latency 600 mhz fir with high-overdrive chargerecovery logic," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1-12, 2011.
14 W. Athas, L. Svensson, and N. Tzartzanis, "A resonant signal driver for two-phase, almost-nonoverlapping clocks," Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., 1996 IEEE International Symposium on, vol.4, pp. 129-132, 12-15 May, 1996.
15 A. Drake, K. Nowka, T. Nguyen, J. Burns, and R. Brown, "Resonant clocking using distributed parasitic capacitance," Solid-State Circuits, IEEE Journal of, vol. 39, no. 9, pp. 1520-1528, sept. 2004.   DOI   ScienceOn
16 B. Mesgarzadeh, M. Hansson, and A. Alvandpour, "Jitter characteristic in charge recovery resonant clock distribution," Solid-State Circuits, IEEE Journal of, vol. 42, no. 7, pp. 1618-1625, july 2007.   DOI   ScienceOn
17 W. Athas, L. Svensson, J. Koller, N. Tzartzanis, and E. Ying-Chin Chou, "Low-power digital systems based on adiabaticswitching principles," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 2, no. 4, pp. 398-407, Dec. 1994.   DOI   ScienceOn
18 V. S. Sathe, J. Y. Chueh, and M. C. Papaefthymiou, "Energy-efficient ghz-class charge-recovery logic," Solid-State Circuits, IEEE Journal of, vol. 42, no. 1, pp. 38-47, Jan. 2007.   DOI   ScienceOn
19 W. H. Ma, J. C. Kao, V. S. Sathe, and M. Papaefthymiou, "A 187MHz subthreshold-supply robust fir filter with charge-recovery logic," VLSI Circuits, 2009 Symposium on, pp. 202-203, June 2009.