Browse > Article
http://dx.doi.org/10.5573/JSTS.2010.10.1.001

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family  

Anuar, Nazrul (Graduate School of Electronical Information & System Engineering, Gifu University)
Takahashi, Yasuhiro (Graduate School of Electronical Information & System Engineering, Gifu University)
Sekine, Toshikazu (Graduate School of Electronical Information & System Engineering, Gifu University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.10, no.1, 2010 , pp. 1-10 More about this Journal
Abstract
This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.
Keywords
Adiabatic logic; low-power; two phase clocked; energy recovery; split-level; power clock generator;
Citations & Related Records

Times Cited By SCOPUS : 8
연도 인용수 순위
1 M. Alioto and G. Palumbo, “Performance evaluation of adiabatic gates,” Circuits and Systems, IEEE Transaction on, Vol.47, Issue 9, Sep., 2000, pp. 1297-1308.   DOI   ScienceOn
2 R.T. Himman, and M.F. Schlecht, “Recovered energy logic-a highly efficient alternative to today’s logic circuits,” Proc. IEEE Power Electron. Specialists Conf., 1993, pp.17-26.
3 V.I. Starosel’skii, “Reversible logic,” Mikroelektronika, Vol.28, Issue 3, 1999, pp. 213-222.
4 K.A. Valiev and V.I. Starosel’skii, “A model and properties of a thermodynamically reversible logic gate,” Mikroelektronika, Vol.29, Issue 2, 2000, pp.83-98.
5 K. Takahashi, and M. Mizunuma, “Adiabatic dynamic CMOS logic circuit,” Electronics and Communications in Japan Part II, vol. 83, Issue 5, April 2000, pp. 50-58   DOI   ScienceOn
6 K. Takahashi, and M. Mizunuma, “Adiabatic dynamic CMOS logic circuit,” IEICE Trans. Electron., Vol. J81-CII, Issue 10, Oct., 1998, pp. 810-817.
7 J. Marjonen, and M. Aberg, “A single clocked adiabatic static logic-a proposal for digital low power applications,” J. VLSI Signal Processing, Vol.27, Issue 27, Feb., 2001, pp. 253-268.   DOI   ScienceOn
8 Y. Ye, and K. Roy, “QSERL: Quasi-static energy recovery logic,” Solid-States Circuits., IEEE Journal, Vol.36, Issue 2, Feb., 2001, pp. 239-248.   DOI   ScienceOn
9 S. Kim, C.H. Ziesler, and M.C. Papaefthymiou, “Charge-recovery computing on silicon,” Computers, IEEE Transactions on, Vol.54, Issue 6, Jun., 2005, pp.651-659.   DOI   ScienceOn
10 V.I. Starosel’skii, “Adiabatic logic circuits: A review,” Russian Microelectronics, Vol. 31, Issue 1, 2002, pp.37-58.   DOI
11 Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, “2PADCL: Two phase drive adiabatic dynamic CMOS logic,” in Proc. IEEE APCCAS, Dec., 2006, pp. 1486-1489.
12 C. Siyong, et al, “Analysis and design of an efficient irreversible energy recovery logic in 0.18-${\mu}m$ CMOS,” Circuits and Systems, IEEE Transactions on, Vol.55, Issue 9, Oct., 2008, pp.2595-2607.   DOI   ScienceOn
13 N. Anuar, Y. Takahashi, and T. Sekine, “Adiabatic logic versus CMOS for low power applications,” Proc. ITC-CSCC 2009, Jul., 2009, pp. 302-305.
14 K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “A leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proc. IEEE, Vol.91, Issue2, Feb., 2003, pp.305-327.   DOI   ScienceOn
15 Y. Moon and D.K. Jeong, “An efficient charge recovery logic circuit,” Solid-States Circuits., IEEE Journal, Vol.31, Issue4, Apr., 1996, pp.514-522.   DOI   ScienceOn
16 W.C. Athas, L.J. Svensson, J.G. Koller, N. Tzartzains, and E. Y-C. Chou, “Low-power digital systems based on adiabatic-switching principles,” Very Large Scale Integration. (VLSI) Syst., IEEE Transaction on, Vol.2, Issue4, Dec., 1994, pp.398-407.   DOI   ScienceOn
17 A Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson, and T.R. Wik, “Adiabatic Computing with the 2N-2N2D logic family,” in Proc. VLSI Circuits Dig. Tech. Papers, IEEE Symposium on, June 1994, pp.25-26.
18 A.G. Dickinson and J.S. Denker, “Adiabatic dynamic logic,” Solid-States Circuits, IEEE Journal, Vol.30, Issue3, Mar., 1995, pp.311-315.   DOI   ScienceOn
19 K.T. Lau and F. Liu, “Improved adiabatic pseudodomino logic,” Electron. Lett. Vol.33, Issue25, 1997, pp.2113-2114.   DOI   ScienceOn