• Journal of the Korean Society of Manufacturing Process Engineers
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• v.14 no.5
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• pp.68-74
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• 2015

In the present work, a series of numerical calculations have been conducted on the cooling of a hot surface using an air/water mist jet. In some cooling processes, such as in the glass-tempering process, direct contact between the cold water drops and the hot surface should be avoided, because this may cause surface cracks due to the sharp temperature gradients. Thus, the main focus of this study is finding the appropriate operating conditions for maximum cooling without direct contact between the drops and the surface. A series of numerical experiments have been performed, and, at the same time, those results were compared with those of the previous experiments for verification purposes. The effects of droplet impinging velocity, hot plate temperature, and liquid loading ratio for mono-dispersed drops of various sizes were studied in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.189-194
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• 2006

Ordered nanostructure materials have received attention due to their unique physical properties and potential applications in electronics, mechanics and optical devices. To actualize most of the proposed applications, it is quite important to obtain highly ordered nanostructure arrays. The well-aligned nanostructure can be achieved by synthesizing nanostructure material in the highly ordered template. To get well-aligned pore array and reduce process time, rapid thermal anneal by an IR lamp was employed in vacuum state at $500^{\circ}C$ for 2 hour. The pore array is comparable to a template annealed in vacuum furnace at $500^{\circ}C$ for 30 hours. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrier layer thickness of 25 nm, the pore depth of $9{\mu}m$, and the pore density of higher than $1.2{\times}10^{10}cm^{-2}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.59-66
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• 1993

PZT thin film deposited by rf magnetron sputtering was annealed by rapid thermal process(RTP) in PbO ambient to prevent vaporing of Pb and interface reactions. Si and TiN/Ti/Si substrates were prepared to survey application of TiN/Ti layer which can prevent interface interaction with Si and crack of PZT thin films. As temperature increased. PZT thin films surface on Si substrate appeared more severe cracks which should affect electrical properties deadly. TiN/Ti(40-150${\mu}{\Omega}{\cdot}cm$) layer applied for buffer layer suppressed interface interaction and film cracking. The measured leakage current(LC) and breakdown voltage(BV) of PZT thin film on TiN/Ti/Si substrate annealed at 650$^{\circ}$C for 15 sec (thickness of 2500$\AA$) were 38 nA/cm2 and 3.5 MV/cm and dielectric constant was 310 at 1 MHz, and remanent polarization (Pr) and coercive field (Ec) were 6.4${\mu}C/cm^{2}$ and 0.2MV/cm at 60 Hz, respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.8
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• pp.325-329
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• 2003

Effects of thermal treatment on the structural properties of diamond-like carbon (DU) films were examined. The DLC films were deposited by using a modified filtered cathodic vacuum arc (FCVA) deposition system and by varying the negative substrate bias voltage, deposition time, and nitrogen flow rate. Thermal treatment on DLC films was performed using a rapid thermal annealing (RTA) process at $600^{\circ}C$ for 2min. Raman spectroscopy, x-ray photoemission spectroscopy (XPS), atomic force microscope (AFM), and surface profiler were used to characterize the I$_{D}$I$_{G}$ intensity ratio, sp$^3$ hybrid carbon fraction, internal stress, and surface roughness. It was found for all the deposited DLC films that the RTA-treatment results in the release of internal compressive stress, while at the same time it leds to the decrease of sp$^3$ fraction and the increase of I$_{D}$I$_{G}$ intensity ratio. It was also suggested that the thermal treatment effect on the structural property of DLC films strongly depends on the diamond-like nature (i.e., sp$^3$ fraction) of as-deposited film.ed film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.27-28
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• 2007

In this paper, Ni-Co alloy was used for improvement of thermal stability of Ni silicide. The proposed Ni/Ni-Co structure exhibited wide temperature window of rapid thermal process. Sheet resistance as well as cross-sectional profile showed stable characteristics in spite of high temperature annealing up to $700^{\circ}C$ for 30min. Therefore, the proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni silicide for nano-scale CMOSFET technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.16-17
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• 2006

In this paper, Ni-V alloy was studied with different structures and thickness. In case of Ni-V and Ni-V/Co/TiN, low resistive Ni silicide was formed after one step RTP (Rapid Thermal Process) with temperature range from $400^{\circ}C$ to $600^{\circ}C$ for 30sec in vacuum. After furnace annealing with temperatures range from $550^{\circ}C$ to $650^{\circ}C$ for 30min in nitrogen ambient, Ni-V single structure shows the best thermal stability compare with the other ones. To enhance the thermal stability up to 650oC and find the optimal thickness of Ni silicide, different thickness of Ni-V was studied in this work. Stable sheet resistance was obtained through Ni-V single structure with optimal Ni-V thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.