• Journal of Powder Materials
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• v.23 no.3
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• pp.235-239
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• 2016

This study is performed to fabricate a Ti porous body by freeze drying process using titanium hydride ($TiH_2$) powder and camphene. Then, the Ti porous body is employed to synthesize carbon nanotubes (CNTs) using thermal catalytic chemical vapor deposition (CCVD) with Fe catalyst and methane ($CH_4$) gas to increase the specific surface area. The synthesized Ti porous body has $100{\mu}M$-sized macropores and $10-30{\mu}m$-sized micropores. The synthesized CNTs have random directions and are entangled with adjacent CNTs. The CNTs have a bamboo-like structure, and their average diameter is about 50 nm. The Fe nano-particles observed at the tip of the CNTs indicate that the tip growth model is applicable. The specific surface area of the CNT-coated Ti porous body is about 20 times larger than that of the raw Ti porous body. These CNT-coated Ti porous bodies are expected to be used as filters or catalyst supports.

• Journal of Microbiology and Biotechnology
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• v.20 no.7
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• pp.1053-1060
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• 2010

Cordyceps militaris, an entomopathogenic fungus belonging to the class Ascomycetes, has been reported to have beneficial biological activities such as hypoglycemic, anti-inflammatory, antitumor, antimetastatic, hypolipidemic, immunomodulatory, and antioxidant effects. In this study, the crude water-soluble polysaccharide CMP, which was obtained from the fruiting body of C. militaris by hot water extraction and ethanol precipitation, was fractionated by DEAE-cellulose and Sepharose CL-6B column chromatographies. This process resulted in three polysaccharide fractions, termed CMP Fr I, CMP Fr II, and CMP Fr III. Of these fractions, CMP Fr II, with an average molecular mass of 127 kDa, was able to upregulate effectively the phenotypic functions of macrophages such as NO production and cytokine expression. The chemical property of the stimulatory polysaccharide, CMP Fr II, was determined based on its monosaccharide composition, which consisted of glucose (56.4%), galactose (26.4%), and mannose (17.2%). Its structural characteristics were investigated by a combination of chemical and instrumental analyses, including methylation, reductive cleavage, acetylation, Fourier transform infrared spectroscopy (FTIR), and gas chromatography-mass spectrometry (GCMS). Results indicated that CMP Fr II consisted of the (1${\rightarrow}$4) or (1${\rightarrow}$2) linked glucopyranosyl or galactopyranosyl residue with a (1${\rightarrow}$2) or (1${\rightarrow}$6) linked mannopyranosyl, glucopyranosyl, or galactopyranosyl residue as a side chain. The configuration of the ${\beta}$-linkage and random coil conformation of CMP Fr II were confirmed using a Fungi-Fluor kit and Congo red reagent, respectively.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• The Journal of the Korea Contents Association
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• v.8 no.1
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• pp.339-347
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• 2008

A balanced game is one where the main determining factor for the success of the player is the skill level of that player Random events can occur, but a better player should be more successful than a poor one unless the player has an unusually long run of bad luck. Balancing a game is a very difficult to define a purpose, and to implement process. The possible ways are somewhat subjective and depend on the nature of the game. This paper provides new algorithm for character adjustment using log function with some nature-based Ideas. The algorithm shows not only how we decide the exact point of character adjustment but also how much we have to modify the parameters for changing abilities of the character. This paper shows the experimental results of the algorithm and shows differences between normal game playing and playing with character adjustment.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Journal of the Korean Institute of Navigation
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• v.12 no.1
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• pp.71-84
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• 1988

For traffic proceeding in random directions on a plane surface the frequency of collision, if no avoiding action in taken ,is approximately proportional to the square of the traffic density and directly proportional to the size and speed of the ship, Avoiding is normally taken and the rte of collisions is therefore also governed by additional factors such as the visibility, the effectiveness of the collisionavoidance rules, the competence of personnel or watchkeeping attitude, the maneuverability of the ship and the efficiency of radar and other equipments. From the viewpoint of watchkeeper who is responsible for maneuvering, watchkeeping attitude such as lookout and action to avoid collision is the most controllable factor among those mentioned above. In practice, according to the investigation of the institution of marine courts, about 50% co collisions occurred is caused by disorbedience to steering and sailing rules of international regulations for preventing collision at sea including lookout. So we classify the process of collisions with first sight of another ship , assessment of risk of collisions and action to avoid collisions and make a factural survey about lookout and action to avoid collisions from the point on "time" and " distance", namely relationship among ship's size, speed, first sight time of another ship, action to avoid collisions ,and distance from sight of another ship to collision occurred. According to the results of the actual survey , we come to conclude that most of collisions occurred are due to improper lookout and ineffective action to avoid collision which means time lag from first sight of another ship to time of action taken to avoid collision is relatively long. is relatively long.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1372-1382
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• 1999

The major source of errors in high-speed networks such as Broadband ISDN(B-lSDN) is buffer overflow during congested conditions. These congestion errors are the dominant sources of errors in 1high-speed networks and result in cell losses. Conventional communication protocols use error detection and retransmission to deal with lost packets and transmission errors. However, these conventional ARQ(Automatic Repeat Request) methods are not suitable for the high-speed networks since the transmission delay due to retransmissions becomes significantly large. As an alternative, we have presented a method to recover consecutive cell losses using forward error correction(FEC) in ATM(Asynchronous Transfer Mode)networks to reduce the problem. The performance estimation based on the cell discard process model has showed our method can reduce the cell loss rate substantially. Also, the performance estimations in ATM networks by interleaving and IP multicast service are discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• KIPS Transactions on Software and Data Engineering
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• v.5 no.8
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• pp.393-400
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• 2016

Recently, there have been various researches on efficient and automatic analysis on urban environment methods that utilize the computer vision and machine learning technology. Among many new analyses, urban safety analysis has received a major attention. In order to predict more accurately on safety score and reflect the human visual perception, it is necessary to consider the generic and local information that are most important to human perception. In this paper, we use Double-column Convolutional Neural network consisting of generic and local columns for the prediction of urban safety. The input of generic and local column used re-sized and random cropped images from original images, respectively. In addition, a new learning method is proposed to solve the problem of over-fitting in a particular column in the learning process. For the performance comparison of our Double-column Convolutional Neural Network, we compare two Support Vector Regression and three Convolutional Neural Network models using Root Mean Square Error and correlation analysis. Our experimental results demonstrate that our Double-column Convolutional Neural Network model show the best performance with Root Mean Square Error of 0.7432 and Pearson/Spearman correlation coefficient of 0.853/0.840.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.464-469
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• 2002

$SrBi_2Nb_2O_9(SBN)$ thin films were grown on Pt/Ti/Si and p-type Si(100) substrates by rf-magnetron co-sputtering method using two ceramic targets, $SrNb_2O_6\; and \;Bi_2O_3$. The structural and electrical characteristics have been investigated to confirm the possibility of the SBN thin films for the applications to destructive and nondestructive read out ferroelectric random access memory(FRAM). For the optimum growth condition X-ray diffraction patterns showed that SBN films had well crystallized Bi-layered perovskite structure after $700^{\circ}C$ heat-treatment in furnace. From this specimen we got remnant polarization $(2P_r)$ of about 6 uC/$\textrm{cm}^2$ and coercive voltage $(V_c)$ of about 1.5 V at an applied voltage of 5 V. The leakage current density was $7.6{\times}10^{-7}$/A/$\textrm{cm}^2$ at an applied voltage of 5V. And for the NDRO-FRAM application, properties of SBN films on Si substrate has been investigated. From transmission electron microscopy (TEM) analysis, we found the furnace treated sample had a native oxide about 2 times thicker than the RTA treated sample and this thick native oxide layer had a bad effect on C-V characteristics of SBN/Si thin film. After $650^{\circ}C$ RTA process, we got the improved memory window of 1.3 V at an applied voltage of 5 V.